Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16985

1

T1

10

T6

337

T8

16

auto[1]

11495

1

T6

310

T18

19

T28

75

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4008	1			T6	193		T13	10		T28	20
values[1]	3349	1			T1	10		T9	8		T28	21
values[2]	3619	1			T6	101		T8	16		T14	12
values[3]	2920	1			T6	68		T28	20		T29	20
values[4]	3499	1			T6	133		T12	16		T19	2
values[5]	3638	1			T6	26		T133	6		T28	22
values[6]	3485	1			T6	86		T29	20		T31	20
values[7]	3962	1			T6	40		T64	8		T82	2

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4553	1			T6	173		T14	12		T28	44
values[1]	3732	1			T6	44		T13	10		T18	20
values[2]	2704	1			T6	60		T9	8		T12	16
values[3]	3284	1			T1	10		T82	2		T29	94
values[4]	4267	1			T6	110		T81	4		T29	90
values[5]	3347	1			T6	129		T64	8		T221	2
values[6]	3338	1			T6	131		T28	88		T29	20
values[7]	3255	1			T8	16		T28	62		T29	29

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	447	1			T6	141		T29	12		T151	12
auto[0]	values[0]	values[1]	284	1			T13	10		T46	15		T118	6
auto[0]	values[0]	values[2]	217	1			T6	9		T29	23		T174	8
auto[0]	values[0]	values[3]	260	1			T37	23		T174	12		T152	21
auto[0]	values[0]	values[4]	330	1			T29	11		T222	14		T37	9
auto[0]	values[0]	values[5]	272	1			T29	12		T118	12		T206	14
auto[0]	values[0]	values[6]	317	1			T6	17		T28	16		T31	13
auto[0]	values[0]	values[7]	385	1			T31	16		T151	11		T223	2
auto[0]	values[1]	values[0]	337	1			T30	9		T174	106		T210	13
auto[0]	values[1]	values[1]	305	1			T224	4		T181	11		T118	25
auto[0]	values[1]	values[2]	265	1			T9	8		T30	15		T151	10
auto[0]	values[1]	values[3]	130	1			T1	10		T118	13		T152	10
auto[0]	values[1]	values[4]	273	1			T180	13		T181	17		T210	9
auto[0]	values[1]	values[5]	349	1			T28	9		T34	11		T196	4
auto[0]	values[1]	values[6]	191	1			T30	11		T35	8		T36	9
auto[0]	values[1]	values[7]	196	1			T34	25		T46	15		T175	9
auto[0]	values[2]	values[0]	320	1			T14	12		T74	4		T37	8
auto[0]	values[2]	values[1]	399	1			T18	8		T29	30		T33	18
auto[0]	values[2]	values[2]	214	1			T175	14		T194	12		T225	14
auto[0]	values[2]	values[3]	177	1			T31	17		T173	24		T150	6
auto[0]	values[2]	values[4]	237	1			T6	7		T226	10		T227	8
auto[0]	values[2]	values[5]	183	1			T6	15		T181	11		T46	14
auto[0]	values[2]	values[6]	347	1			T28	43		T151	10		T36	10
auto[0]	values[2]	values[7]	263	1			T8	16		T28	11		T29	20
auto[0]	values[3]	values[0]	197	1			T6	17		T32	14		T34	12
auto[0]	values[3]	values[1]	166	1			T35	13		T227	9		T190	13
auto[0]	values[3]	values[2]	264	1			T195	8		T181	12		T210	9
auto[0]	values[3]	values[3]	212	1			T29	11		T35	17		T36	9
auto[0]	values[3]	values[4]	163	1			T31	7		T174	32		T210	14
auto[0]	values[3]	values[5]	285	1			T6	7		T30	9		T31	8
auto[0]	values[3]	values[6]	76	1			T35	19		T36	11		T37	7
auto[0]	values[3]	values[7]	131	1			T28	9		T32	5		T210	16
auto[0]	values[4]	values[0]	301	1			T31	11		T49	2		T173	10
auto[0]	values[4]	values[1]	133	1			T33	11		T34	13		T174	14
auto[0]	values[4]	values[2]	118	1			T6	15		T12	16		T19	2
auto[0]	values[4]	values[3]	282	1			T30	44		T31	11		T32	10
auto[0]	values[4]	values[4]	266	1			T6	9		T29	13		T36	11
auto[0]	values[4]	values[5]	292	1			T28	22		T32	15		T33	13
auto[0]	values[4]	values[6]	394	1			T6	9		T29	16		T30	128
auto[0]	values[4]	values[7]	338	1			T36	9		T180	14		T173	9
auto[0]	values[5]	values[0]	369	1			T35	13		T46	11		T114	20
auto[0]	values[5]	values[1]	168	1			T32	14		T220	48		T46	12
auto[0]	values[5]	values[2]	256	1			T151	11		T197	22		T210	11
auto[0]	values[5]	values[3]	232	1			T70	4		T151	11		T228	2
auto[0]	values[5]	values[4]	477	1			T6	9		T36	26		T46	16
auto[0]	values[5]	values[5]	168	1			T133	6		T229	10		T230	16
auto[0]	values[5]	values[6]	296	1			T31	14		T34	11		T50	18
auto[0]	values[5]	values[7]	232	1			T28	11		T33	11		T34	13
auto[0]	values[6]	values[0]	474	1			T151	11		T37	9		T231	2
auto[0]	values[6]	values[1]	399	1			T6	35		T37	15		T46	9
auto[0]	values[6]	values[2]	74	1			T6	12		T181	12		T184	8
auto[0]	values[6]	values[3]	144	1			T31	16		T180	14		T232	11
auto[0]	values[6]	values[4]	382	1			T29	19		T35	6		T174	18
auto[0]	values[6]	values[5]	155	1			T152	17		T170	11		T187	7
auto[0]	values[6]	values[6]	224	1			T6	13		T53	2		T35	14
auto[0]	values[6]	values[7]	200	1			T32	13		T118	13		T152	5
auto[0]	values[7]	values[0]	381	1			T28	33		T233	12		T35	11
auto[0]	values[7]	values[1]	298	1			T29	53		T34	14		T36	19
auto[0]	values[7]	values[2]	241	1			T18	15		T151	17		T173	42
auto[0]	values[7]	values[3]	357	1			T82	2		T29	63		T31	12
auto[0]	values[7]	values[4]	502	1			T6	22		T81	4		T29	13
auto[0]	values[7]	values[5]	186	1			T64	8		T221	2		T29	30
auto[0]	values[7]	values[6]	292	1			T28	14		T32	42		T173	40
auto[0]	values[7]	values[7]	162	1			T35	12		T234	18		T235	18
auto[1]	values[0]	values[0]	141	1			T6	12		T29	12		T151	19
auto[1]	values[0]	values[1]	241	1			T46	25		T118	89		T207	13
auto[1]	values[0]	values[2]	152	1			T6	11		T29	5		T174	29
auto[1]	values[0]	values[3]	191	1			T37	5		T174	8		T152	7
auto[1]	values[0]	values[4]	220	1			T29	11		T37	15		T46	4
auto[1]	values[0]	values[5]	207	1			T29	8		T118	8		T206	13
auto[1]	values[0]	values[6]	205	1			T6	3		T28	4		T31	7
auto[1]	values[0]	values[7]	139	1			T31	24		T151	11		T36	11
auto[1]	values[1]	values[0]	181	1			T30	22		T174	14		T210	7
auto[1]	values[1]	values[1]	171	1			T181	9		T118	9		T236	57
auto[1]	values[1]	values[2]	100	1			T30	5		T151	13		T34	9
auto[1]	values[1]	values[3]	266	1			T118	7		T152	31		T141	7
auto[1]	values[1]	values[4]	156	1			T180	7		T181	3		T210	11
auto[1]	values[1]	values[5]	133	1			T28	12		T34	9		T237	6
auto[1]	values[1]	values[6]	163	1			T30	9		T35	12		T36	11
auto[1]	values[1]	values[7]	133	1			T34	15		T46	5		T175	11
auto[1]	values[2]	values[0]	257	1			T37	12		T150	50		T184	1
auto[1]	values[2]	values[1]	209	1			T18	12		T29	12		T33	3
auto[1]	values[2]	values[2]	178	1			T175	39		T194	9		T225	6
auto[1]	values[2]	values[3]	195	1			T31	106		T173	24		T150	14
auto[1]	values[2]	values[4]	100	1			T6	13		T227	13		T185	10
auto[1]	values[2]	values[5]	280	1			T6	66		T181	13		T46	6
auto[1]	values[2]	values[6]	70	1			T28	3		T151	11		T36	10
auto[1]	values[2]	values[7]	190	1			T28	9		T29	9		T32	14
auto[1]	values[3]	values[0]	83	1			T6	3		T32	6		T34	14
auto[1]	values[3]	values[1]	237	1			T35	7		T227	12		T190	23
auto[1]	values[3]	values[2]	207	1			T181	8		T210	11		T177	8
auto[1]	values[3]	values[3]	154	1			T29	9		T35	8		T36	11
auto[1]	values[3]	values[4]	193	1			T31	25		T174	8		T210	11
auto[1]	values[3]	values[5]	224	1			T6	41		T30	17		T31	12
auto[1]	values[3]	values[6]	109	1			T35	9		T36	9		T37	13
auto[1]	values[3]	values[7]	219	1			T28	11		T32	47		T210	103
auto[1]	values[4]	values[0]	308	1			T31	10		T173	10		T118	8
auto[1]	values[4]	values[1]	99	1			T33	9		T34	7		T174	6
auto[1]	values[4]	values[2]	65	1			T6	5		T31	14		T46	9
auto[1]	values[4]	values[3]	105	1			T30	5		T31	11		T32	10
auto[1]	values[4]	values[4]	263	1			T6	15		T29	12		T36	9
auto[1]	values[4]	values[5]	198	1			T28	6		T32	5		T33	7
auto[1]	values[4]	values[6]	163	1			T6	80		T29	4		T30	8
auto[1]	values[4]	values[7]	174	1			T36	11		T180	7		T173	11
auto[1]	values[5]	values[0]	225	1			T35	7		T238	8		T46	9
auto[1]	values[5]	values[1]	75	1			T32	6		T46	10		T175	24
auto[1]	values[5]	values[2]	133	1			T151	9		T210	9		T118	13
auto[1]	values[5]	values[3]	251	1			T151	21		T170	25		T194	7
auto[1]	values[5]	values[4]	288	1			T6	17		T36	6		T46	4
auto[1]	values[5]	values[5]	88	1			T229	10		T202	30		T239	9
auto[1]	values[5]	values[6]	114	1			T31	16		T34	21		T36	6
auto[1]	values[5]	values[7]	266	1			T28	11		T33	9		T34	7
auto[1]	values[6]	values[0]	223	1			T151	50		T37	11		T170	28
auto[1]	values[6]	values[1]	284	1			T6	9		T37	11		T46	71
auto[1]	values[6]	values[2]	98	1			T6	8		T181	9		T184	55
auto[1]	values[6]	values[3]	143	1			T31	4		T180	10		T240	28
auto[1]	values[6]	values[4]	178	1			T29	1		T35	29		T174	6
auto[1]	values[6]	values[5]	116	1			T83	8		T152	3		T170	9
auto[1]	values[6]	values[6]	243	1			T6	9		T35	27		T210	7
auto[1]	values[6]	values[7]	148	1			T32	7		T118	35		T152	15
auto[1]	values[7]	values[0]	309	1			T28	11		T35	9		T46	9
auto[1]	values[7]	values[1]	264	1			T29	12		T34	9		T241	2
auto[1]	values[7]	values[2]	122	1			T18	7		T151	12		T173	20
auto[1]	values[7]	values[3]	185	1			T29	11		T31	8		T35	10
auto[1]	values[7]	values[4]	239	1			T6	18		T29	10		T180	6
auto[1]	values[7]	values[5]	211	1			T29	8		T173	9		T174	4
auto[1]	values[7]	values[6]	134	1			T28	8		T32	10		T173	6
auto[1]	values[7]	values[7]	79	1			T35	8		T242	16		T235	26