Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	397	1			T6	7		T13	4		T28	3
auto[ReadAddrCrossIntoMailbox]	272	1			T6	5		T18	1		T28	5
auto[ReadAddrCrossOutOfMailbox]	272	1			T6	2		T18	1		T28	5
auto[ReadAddrCrossAllMailbox]	201	1			T6	4		T28	5		T29	3
auto[ReadAddrOutsideMailbox]	3291	1			T6	43		T8	8		T9	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2201

1

T6

23

T8

4

T9

1

auto[1]

2232

1

T6

38

T8

4

T9

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	705	1			T6	9		T18	2		T28	9
read_ops[0x0b]	749	1			T6	8		T18	3		T28	10
read_ops[0x3b]	740	1			T6	11		T8	2		T9	2
read_ops[0x6b]	749	1			T6	9		T8	4		T13	2
read_ops[0xbb]	746	1			T6	16		T13	2		T28	12
read_ops[0xeb]	744	1			T6	8		T8	2		T19	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T6	1		T32	1		T33	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T6	1		T29	2		T151	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T6	1		T31	1		T33	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T6	1		T28	2		T36	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T33	1		T35	1		T174	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	17	1			T32	1		T37	1		T173	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T28	1		T46	1		T152	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T35	1		T193	1		T243	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	264	1			T6	2		T18	1		T28	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	253	1			T6	3		T18	1		T28	5
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T6	1		T30	1		T32	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T28	1		T30	1		T151	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T29	1		T37	1		T180	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T6	1		T18	1		T31	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T29	1		T30	1		T34	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T18	1		T29	1		T33	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T29	1		T31	1		T34	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T28	1		T36	1		T194	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	253	1			T28	1		T29	1		T31	5
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	300	1			T6	6		T18	1		T28	7
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T30	1		T33	1		T35	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T180	1		T181	2		T46	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T32	1		T36	1		T173	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T28	1		T180	1		T232	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T33	1		T37	1		T210	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T28	1		T29	1		T35	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T151	1		T33	1		T175	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T6	1		T29	1		T31	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	269	1			T6	6		T8	1		T9	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	290	1			T6	4		T8	1		T9	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T13	1		T28	1		T151	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T6	2		T13	1		T50	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T29	3		T30	1		T151	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	17	1			T30	1		T35	1		T37	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T30	4		T36	2		T181	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T28	1		T29	1		T33	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T28	2		T180	1		T46	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T6	1		T28	1		T32	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	278	1			T6	2		T8	2		T29	7
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	279	1			T6	4		T8	2		T28	3
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T6	1		T13	1		T34	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T13	1		T28	1		T29	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T28	2		T151	2		T36	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	13	1			T6	1		T29	1		T31	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T28	1		T32	1		T174	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T6	2		T28	1		T31	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T34	1		T173	1		T152	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T6	1		T29	1		T30	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	305	1			T6	6		T28	5		T74	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	253	1			T6	5		T28	2		T74	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T29	3		T151	1		T35	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T6	1		T32	1		T173	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T151	1		T32	2		T33	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T6	1		T30	1		T151	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T28	1		T29	1		T30	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T31	2		T232	1		T244	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T6	1		T151	1		T53	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T53	1		T173	1		T79	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	281	1			T6	2		T8	1		T19	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	266	1			T6	3		T8	1		T19	1