Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2428443	1			T1	126		T2	2		T3	15
all_pins[1]	2428443	1			T1	126		T2	2		T3	15
all_pins[2]	2428443	1			T1	126		T2	2		T3	15
all_pins[3]	2428443	1			T1	126		T2	2		T3	15
all_pins[4]	2428443	1			T1	126		T2	2		T3	15
all_pins[5]	2428443	1			T1	126		T2	2		T3	15
all_pins[6]	2428443	1			T1	126		T2	2		T3	15
all_pins[7]	2428443	1			T1	126		T2	2		T3	15

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	19420303	1			T1	1008		T2	16		T3	120
values[0x1]	7241	1			T6	144		T10	10		T26	4591
transitions[0x0=>0x1]	6508	1			T6	144		T10	4		T26	4184
transitions[0x1=>0x0]	6513	1			T6	144		T10	4		T26	4184

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2427948	1			T1	126		T2	2		T3	15
all_pins[0]	values[0x1]	495	1			T6	140		T10	3		T26	6
all_pins[0]	transitions[0x0=>0x1]	451	1			T6	140		T10	2		T26	4
all_pins[0]	transitions[0x1=>0x0]	146	1			T26	6		T34	3		T149	4
all_pins[1]	values[0x0]	2428253	1			T1	126		T2	2		T3	15
all_pins[1]	values[0x1]	190	1			T10	1		T26	8		T34	3
all_pins[1]	transitions[0x0=>0x1]	131	1			T26	8		T34	1		T149	2
all_pins[1]	transitions[0x1=>0x0]	241	1			T10	1		T26	1		T62	1
all_pins[2]	values[0x0]	2428143	1			T1	126		T2	2		T3	15
all_pins[2]	values[0x1]	300	1			T10	2		T26	1		T62	1
all_pins[2]	transitions[0x0=>0x1]	254	1			T10	1		T26	1		T62	1
all_pins[2]	transitions[0x1=>0x0]	131	1			T6	2		T26	4		T149	4
all_pins[3]	values[0x0]	2428266	1			T1	126		T2	2		T3	15
all_pins[3]	values[0x1]	177	1			T6	2		T10	1		T26	4
all_pins[3]	transitions[0x0=>0x1]	133	1			T6	2		T149	6		T112	4
all_pins[3]	transitions[0x1=>0x0]	155	1			T26	7		T62	1		T34	5
all_pins[4]	values[0x0]	2428244	1			T1	126		T2	2		T3	15
all_pins[4]	values[0x1]	199	1			T10	1		T26	11		T62	1
all_pins[4]	transitions[0x0=>0x1]	153	1			T10	1		T26	8		T62	1
all_pins[4]	transitions[0x1=>0x0]	1324	1			T26	396		T34	1		T149	4
all_pins[5]	values[0x0]	2427073	1			T1	126		T2	2		T3	15
all_pins[5]	values[0x1]	1370	1			T26	399		T34	2		T149	5
all_pins[5]	transitions[0x0=>0x1]	946	1			T26	5		T34	2		T149	5
all_pins[5]	transitions[0x1=>0x0]	3898	1			T26	3761		T62	1		T34	1
all_pins[6]	values[0x0]	2424121	1			T1	126		T2	2		T3	15
all_pins[6]	values[0x1]	4322	1			T26	4155		T62	1		T34	1
all_pins[6]	transitions[0x0=>0x1]	4291	1			T26	4152		T62	1		T149	1
all_pins[6]	transitions[0x1=>0x0]	157	1			T6	2		T10	2		T26	4
all_pins[7]	values[0x0]	2428255	1			T1	126		T2	2		T3	15
all_pins[7]	values[0x1]	188	1			T6	2		T10	2		T26	7
all_pins[7]	transitions[0x0=>0x1]	149	1			T6	2		T26	6		T62	2
all_pins[7]	transitions[0x1=>0x0]	461	1			T6	140		T10	1		T26	5