Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3384	1			T6	44		T13	10		T28	46
values[1]	4404	1			T6	48		T8	16		T28	20
values[2]	3733	1			T6	40		T9	8		T14	12
values[3]	2981	1			T6	109		T82	2		T28	61
values[4]	3487	1			T6	123		T18	22		T28	28
values[5]	3843	1			T1	10		T6	257		T221	2
values[6]	3735	1			T6	26		T64	8		T18	20
values[7]	2913	1			T12	16		T74	4		T29	38

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3960	1			T9	8		T28	28		T81	4
values[1]	3131	1			T6	20		T18	22		T133	6
values[2]	4137	1			T6	157		T82	2		T221	2
values[3]	3417	1			T13	10		T14	12		T28	20
values[4]	3428	1			T1	10		T6	68		T19	2
values[5]	3601	1			T6	193		T8	16		T28	42
values[6]	3559	1			T6	107		T18	20		T28	46
values[7]	3247	1			T6	102		T12	16		T28	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28040

1

T1

10

T6

635

T8

16

auto[1]

440

1

T6

12

T28

1

T29

4

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	501	1			T30	136		T152	20		T245	14
auto[0]	values[0]	values[1]	325	1			T29	29		T184	20		T246	42
auto[0]	values[0]	values[2]	414	1			T6	24		T29	41		T31	41
auto[0]	values[0]	values[3]	444	1			T13	10		T46	52		T118	53
auto[0]	values[0]	values[4]	385	1			T29	27		T32	50		T210	20
auto[0]	values[0]	values[5]	521	1			T6	20		T151	20		T34	23
auto[0]	values[0]	values[6]	447	1			T28	46		T31	20		T32	50
auto[0]	values[0]	values[7]	306	1			T29	74		T242	14		T175	33
auto[0]	values[1]	values[0]	722	1			T29	65		T234	18		T46	66
auto[0]	values[1]	values[1]	449	1			T28	20		T32	20		T36	20
auto[0]	values[1]	values[2]	730	1			T31	32		T34	40		T35	33
auto[0]	values[1]	values[3]	665	1			T33	20		T174	115		T152	20
auto[0]	values[1]	values[4]	541	1			T6	45		T151	29		T36	20
auto[0]	values[1]	values[5]	365	1			T8	16		T34	48		T210	20
auto[0]	values[1]	values[6]	662	1			T173	30		T177	8		T46	20
auto[0]	values[1]	values[7]	182	1			T29	20		T36	20		T180	24
auto[0]	values[2]	values[0]	477	1			T9	8		T34	20		T46	33
auto[0]	values[2]	values[1]	293	1			T34	20		T174	20		T247	8
auto[0]	values[2]	values[2]	693	1			T31	20		T33	20		T180	22
auto[0]	values[2]	values[3]	505	1			T14	12		T32	20		T37	41
auto[0]	values[2]	values[4]	393	1			T6	20		T19	2		T223	2
auto[0]	values[2]	values[5]	388	1			T32	20		T80	8		T237	81
auto[0]	values[2]	values[6]	430	1			T180	20		T179	20		T141	45
auto[0]	values[2]	values[7]	498	1			T6	19		T29	42		T34	29
auto[0]	values[3]	values[0]	387	1			T81	4		T151	21		T173	28
auto[0]	values[3]	values[1]	292	1			T30	31		T34	23		T36	43
auto[0]	values[3]	values[2]	564	1			T6	89		T82	2		T35	19
auto[0]	values[3]	values[3]	254	1			T31	20		T36	18		T206	27
auto[0]	values[3]	values[4]	472	1			T28	21		T181	20		T174	57
auto[0]	values[3]	values[5]	317	1			T28	20		T32	28		T194	23
auto[0]	values[3]	values[6]	258	1			T185	21		T170	33		T235	20
auto[0]	values[3]	values[7]	392	1			T6	20		T28	20		T36	18
auto[0]	values[4]	values[0]	458	1			T28	28		T46	87		T118	93
auto[0]	values[4]	values[1]	407	1			T6	20		T18	22		T29	41
auto[0]	values[4]	values[2]	398	1			T30	20		T31	22		T36	20
auto[0]	values[4]	values[3]	458	1			T151	32		T35	19		T36	32
auto[0]	values[4]	values[4]	444	1			T31	29		T49	2		T194	69
auto[0]	values[4]	values[5]	371	1			T33	20		T50	18		T78	4
auto[0]	values[4]	values[6]	439	1			T6	81		T70	4		T83	8
auto[0]	values[4]	values[7]	469	1			T6	22		T29	25		T33	20
auto[0]	values[5]	values[0]	313	1			T34	19		T37	27		T174	20
auto[0]	values[5]	values[1]	448	1			T133	6		T53	2		T224	4
auto[0]	values[5]	values[2]	674	1			T6	43		T221	2		T28	21
auto[0]	values[5]	values[3]	358	1			T210	33		T194	23		T179	20
auto[0]	values[5]	values[4]	418	1			T1	10		T35	25		T174	24
auto[0]	values[5]	values[5]	625	1			T6	168		T35	20		T36	20
auto[0]	values[5]	values[6]	429	1			T210	20		T46	59		T150	23
auto[0]	values[5]	values[7]	508	1			T6	38		T186	12		T152	26
auto[0]	values[6]	values[0]	757	1			T30	47		T32	20		T222	14
auto[0]	values[6]	values[1]	530	1			T36	110		T175	20		T248	4
auto[0]	values[6]	values[2]	370	1			T28	24		T79	14		T249	22
auto[0]	values[6]	values[3]	214	1			T28	20		T228	2		T173	20
auto[0]	values[6]	values[4]	439	1			T64	8		T29	20		T32	20
auto[0]	values[6]	values[5]	482	1			T28	22		T151	31		T233	12
auto[0]	values[6]	values[6]	476	1			T6	26		T18	20		T250	6
auto[0]	values[6]	values[7]	418	1			T31	19		T46	20		T118	48
auto[0]	values[7]	values[0]	294	1			T151	22		T36	19		T37	29
auto[0]	values[7]	values[1]	347	1			T34	19		T180	21		T175	28
auto[0]	values[7]	values[2]	234	1			T251	16		T46	20		T252	14
auto[0]	values[7]	values[3]	457	1			T30	25		T31	20		T151	21
auto[0]	values[7]	values[4]	286	1			T30	20		T152	21		T185	20
auto[0]	values[7]	values[5]	460	1			T31	121		T35	17		T241	2
auto[0]	values[7]	values[6]	369	1			T29	38		T37	24		T46	54
auto[0]	values[7]	values[7]	418	1			T12	16		T74	4		T35	20
auto[1]	values[0]	values[0]	5	1			T189	3		T236	1		T253	1
auto[1]	values[0]	values[1]	2	1			T22	2		-	-		-	-
auto[1]	values[0]	values[2]	5	1			T29	1		T210	1		T189	2
auto[1]	values[0]	values[3]	7	1			T46	2		T254	4		T239	1
auto[1]	values[0]	values[4]	7	1			T29	1		T32	2		T225	2
auto[1]	values[0]	values[5]	5	1			T211	2		T254	2		T255	1
auto[1]	values[0]	values[6]	5	1			T32	2		T184	1		T256	1
auto[1]	values[0]	values[7]	5	1			T242	2		T150	2		T257	1
auto[1]	values[1]	values[0]	7	1			T141	1		T258	2		T259	1
auto[1]	values[1]	values[1]	3	1			T36	1		T260	1		T47	1
auto[1]	values[1]	values[2]	15	1			T35	2		T237	5		T188	1
auto[1]	values[1]	values[3]	24	1			T174	5		T175	2		T194	1
auto[1]	values[1]	values[4]	12	1			T6	3		T46	4		T261	2
auto[1]	values[1]	values[5]	16	1			T34	1		T150	2		T189	3
auto[1]	values[1]	values[6]	7	1			T249	1		T211	3		T262	1
auto[1]	values[1]	values[7]	4	1			T150	1		T263	3		-	-
auto[1]	values[2]	values[0]	4	1			T170	1		T259	1		T255	2
auto[1]	values[2]	values[1]	3	1			T34	1		T264	1		T256	1
auto[1]	values[2]	values[2]	7	1			T33	1		T175	1		T184	1
auto[1]	values[2]	values[3]	4	1			T37	1		T141	1		T265	1
auto[1]	values[2]	values[4]	10	1			T37	4		T152	2		T227	1
auto[1]	values[2]	values[5]	10	1			T184	1		T257	2		T254	1
auto[1]	values[2]	values[6]	4	1			T218	3		T253	1		-	-
auto[1]	values[2]	values[7]	14	1			T6	1		T29	1		T34	3
auto[1]	values[3]	values[0]	6	1			T151	2		T118	1		T266	1
auto[1]	values[3]	values[1]	10	1			T34	3		T36	2		T213	1
auto[1]	values[3]	values[2]	4	1			T35	1		T181	1		T267	1
auto[1]	values[3]	values[3]	7	1			T36	2		T202	3		T47	2
auto[1]	values[3]	values[4]	2	1			T174	1		T268	1		-	-
auto[1]	values[3]	values[5]	6	1			T269	1		T236	1		T270	4
auto[1]	values[3]	values[6]	5	1			T170	1		T271	4		-	-
auto[1]	values[3]	values[7]	5	1			T36	2		T184	1		T188	1
auto[1]	values[4]	values[0]	5	1			T46	1		T118	2		T199	2
auto[1]	values[4]	values[1]	7	1			T29	1		T184	4		T207	2
auto[1]	values[4]	values[2]	8	1			T175	3		T249	1		T272	1
auto[1]	values[4]	values[3]	4	1			T35	1		T141	1		T263	1
auto[1]	values[4]	values[4]	6	1			T31	1		T194	1		T273	1
auto[1]	values[4]	values[5]	1	1			T274	1		-	-		-	-
auto[1]	values[4]	values[6]	6	1			T174	3		T257	3		-	-
auto[1]	values[4]	values[7]	6	1			T275	2		T218	2		T276	2
auto[1]	values[5]	values[0]	9	1			T34	1		T37	1		T202	2
auto[1]	values[5]	values[1]	8	1			T207	2		T171	2		T277	1
auto[1]	values[5]	values[2]	15	1			T6	1		T28	1		T151	2
auto[1]	values[5]	values[3]	8	1			T194	1		T189	1		T260	1
auto[1]	values[5]	values[4]	2	1			T218	1		T278	1		-	-
auto[1]	values[5]	values[5]	10	1			T6	5		T267	1		T274	1
auto[1]	values[5]	values[6]	9	1			T46	1		T22	1		T239	3
auto[1]	values[5]	values[7]	9	1			T6	2		T152	1		T175	1
auto[1]	values[6]	values[0]	6	1			T30	2		T185	1		T277	1
auto[1]	values[6]	values[1]	6	1			T36	3		T236	3		-	-
auto[1]	values[6]	values[2]	3	1			T249	1		T185	2		-	-
auto[1]	values[6]	values[3]	1	1			T201	1		-	-		-	-
auto[1]	values[6]	values[4]	8	1			T35	3		T265	2		T22	2
auto[1]	values[6]	values[5]	9	1			T118	2		T194	4		T187	2
auto[1]	values[6]	values[6]	8	1			T174	1		T211	2		T236	1
auto[1]	values[6]	values[7]	8	1			T31	1		T211	2		T199	1
auto[1]	values[7]	values[0]	9	1			T36	1		T37	2		T263	1
auto[1]	values[7]	values[1]	1	1			T34	1		-	-		-	-
auto[1]	values[7]	values[2]	3	1			T202	2		T279	1		-	-
auto[1]	values[7]	values[3]	7	1			T30	1		T37	2		T235	2
auto[1]	values[7]	values[4]	3	1			T152	1		T22	1		T202	1
auto[1]	values[7]	values[5]	15	1			T31	2		T35	3		T240	2
auto[1]	values[7]	values[6]	5	1			T46	3		T269	1		T188	1
auto[1]	values[7]	values[7]	5	1			T174	1		T178	3		T266	1