Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1910

1

T6

9

T7

1

T10

1

auto[1]

1837

1

T6

11

T10

1

T11

4

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2079

1

T6

17

T7

1

T10

2

auto[1]

1668

1

T6

3

T11

10

T15

12

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2958

1

T6

15

T11

10

T15

12

auto[1]

789

1

T6

5

T7

1

T10

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	718	1			T6	1		T10	1		T11	2
valid[1]	768	1			T6	5		T11	2		T15	3
valid[2]	726	1			T6	6		T11	2		T15	2
valid[3]	743	1			T6	4		T10	1		T11	2
valid[4]	792	1			T6	4		T7	1		T11	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	125	1			T6	1		T20	1		T29	1
auto[0]	auto[0]	valid[0]	auto[1]	175	1			T11	1		T15	3		T17	2
auto[0]	auto[0]	valid[1]	auto[0]	137	1			T6	1		T20	1		T23	3
auto[0]	auto[0]	valid[1]	auto[1]	154	1			T11	2		T15	1		T301	1
auto[0]	auto[0]	valid[2]	auto[0]	119	1			T6	1		T20	1		T23	1
auto[0]	auto[0]	valid[2]	auto[1]	183	1			T6	1		T17	1		T44	1
auto[0]	auto[0]	valid[3]	auto[0]	133	1			T26	2		T28	3		T71	1
auto[0]	auto[0]	valid[3]	auto[1]	157	1			T11	1		T62	1		T35	1
auto[0]	auto[0]	valid[4]	auto[0]	141	1			T6	1		T28	1		T44	1
auto[0]	auto[0]	valid[4]	auto[1]	182	1			T6	1		T11	2		T15	1
auto[0]	auto[1]	valid[0]	auto[0]	118	1			T20	1		T71	1		T31	2
auto[0]	auto[1]	valid[0]	auto[1]	156	1			T11	1		T15	1		T44	2
auto[0]	auto[1]	valid[1]	auto[0]	139	1			T6	1		T20	2		T23	2
auto[0]	auto[1]	valid[1]	auto[1]	165	1			T15	2		T288	1		T302	1
auto[0]	auto[1]	valid[2]	auto[0]	120	1			T6	2		T23	1		T28	1
auto[0]	auto[1]	valid[2]	auto[1]	164	1			T6	1		T11	2		T15	2
auto[0]	auto[1]	valid[3]	auto[0]	128	1			T6	3		T26	1		T28	2
auto[0]	auto[1]	valid[3]	auto[1]	164	1			T11	1		T15	2		T62	1
auto[0]	auto[1]	valid[4]	auto[0]	130	1			T6	2		T20	1		T23	1
auto[0]	auto[1]	valid[4]	auto[1]	168	1			T24	1		T45	1		T288	1
auto[1]	auto[0]	valid[0]	auto[0]	76	1			T10	1		T28	1		T32	1
auto[1]	auto[0]	valid[1]	auto[0]	90	1			T6	2		T23	1		T24	1
auto[1]	auto[0]	valid[2]	auto[0]	74	1			T291	1		T62	2		T33	1
auto[1]	auto[0]	valid[3]	auto[0]	73	1			T6	1		T18	1		T23	1
auto[1]	auto[0]	valid[4]	auto[0]	91	1			T7	1		T20	1		T23	1
auto[1]	auto[1]	valid[0]	auto[0]	68	1			T18	1		T20	1		T26	1
auto[1]	auto[1]	valid[1]	auto[0]	83	1			T6	1		T28	1		T45	1
auto[1]	auto[1]	valid[2]	auto[0]	66	1			T6	1		T20	1		T45	1
auto[1]	auto[1]	valid[3]	auto[0]	88	1			T10	1		T20	2		T44	2
auto[1]	auto[1]	valid[4]	auto[0]	80	1			T23	1		T32	1		T62	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal