Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51756

1

T3

3

T6

410

T7

7

auto[1]

17410

1

T6

71

T11

10

T15

12

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50299

1

T3

2

T6

332

T7

3

auto[1]

18867

1

T3

1

T6

149

T7

4

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35932	1			T3	2		T6	252		T7	1
others[1]	5646	1			T6	39		T7	1		T10	8
others[2]	5761	1			T3	1		T6	30		T7	2
others[3]	6408	1			T6	47		T7	1		T10	10
interest[1]	3894	1			T6	40		T10	10		T17	3
interest[4]	23440	1			T3	1		T6	179		T7	1
interest[64]	11525	1			T6	73		T7	2		T10	37

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	17088	1			T3	2		T6	151		T7	1
auto[0]	auto[0]	others[1]	2662	1			T6	17		T10	5		T18	1
auto[0]	auto[0]	others[2]	2762	1			T6	17		T7	2		T10	9
auto[0]	auto[0]	others[3]	3023	1			T6	24		T10	6		T18	4
auto[0]	auto[0]	interest[1]	1863	1			T6	17		T10	6		T18	3
auto[0]	auto[0]	interest[4]	11152	1			T3	1		T6	106		T7	1
auto[0]	auto[0]	interest[64]	5491	1			T6	35		T10	30		T18	5
auto[0]	auto[1]	others[0]	9169	1			T6	35		T11	10		T15	12
auto[0]	auto[1]	others[1]	1422	1			T6	8		T17	6		T24	1
auto[0]	auto[1]	others[2]	1415	1			T6	3		T17	8		T44	2
auto[0]	auto[1]	others[3]	1593	1			T6	8		T17	11		T24	2
auto[0]	auto[1]	interest[1]	992	1			T6	6		T17	3		T24	1
auto[0]	auto[1]	interest[4]	6072	1			T6	27		T11	10		T15	12
auto[0]	auto[1]	interest[64]	2819	1			T6	11		T17	21		T24	3
auto[1]	auto[0]	others[0]	9675	1			T6	66		T10	27		T18	9
auto[1]	auto[0]	others[1]	1562	1			T6	14		T7	1		T10	3
auto[1]	auto[0]	others[2]	1584	1			T3	1		T6	10		T10	2
auto[1]	auto[0]	others[3]	1792	1			T6	15		T7	1		T10	4
auto[1]	auto[0]	interest[1]	1039	1			T6	17		T10	4		T20	6
auto[1]	auto[0]	interest[4]	6216	1			T6	46		T10	19		T18	5
auto[1]	auto[0]	interest[64]	3215	1			T6	27		T7	2		T10	7

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal