Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	840	1			T6	4		T10	4		T26	18
all_values[1]	840	1			T6	4		T10	4		T26	18
all_values[2]	840	1			T6	4		T10	4		T26	18
all_values[3]	840	1			T6	4		T10	4		T26	18
all_values[4]	840	1			T6	4		T10	4		T26	18
all_values[5]	840	1			T6	4		T10	4		T26	18
all_values[6]	840	1			T6	4		T10	4		T26	18
all_values[7]	840	1			T6	4		T10	4		T26	18

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3550

1

T6

17

T10

16

T26

89

auto[1]

3170

1

T6

15

T10

16

T26

55

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2691

1

T6

11

T10

14

T26

51

auto[1]

4029

1

T6

21

T10

18

T26

93

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3793

1

T6

19

T10

18

T26

77

auto[1]

2927

1

T6

13

T10

14

T26

67

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	172	1			T10	1		T26	5		T34	1
all_values[0]	auto[0]	auto[0]	auto[1]	76	1			T26	2		T62	1		T34	2
all_values[0]	auto[0]	auto[1]	auto[0]	144	1			T6	2		T26	2		T34	2
all_values[0]	auto[0]	auto[1]	auto[1]	84	1			T10	1		T26	2		T34	2
all_values[0]	auto[1]	auto[0]	auto[1]	194	1			T6	1		T10	1		T26	5
all_values[0]	auto[1]	auto[1]	auto[1]	170	1			T6	1		T10	1		T26	2
all_values[1]	auto[0]	auto[0]	auto[0]	172	1			T6	1		T10	1		T26	6
all_values[1]	auto[0]	auto[0]	auto[1]	76	1			T6	1		T26	1		T34	4
all_values[1]	auto[0]	auto[1]	auto[0]	151	1			T6	1		T10	1		T149	3
all_values[1]	auto[0]	auto[1]	auto[1]	85	1			T26	3		T34	1		T149	3
all_values[1]	auto[1]	auto[0]	auto[1]	180	1			T6	1		T10	1		T26	7
all_values[1]	auto[1]	auto[1]	auto[1]	176	1			T10	1		T26	1		T34	3
all_values[2]	auto[0]	auto[0]	auto[0]	167	1			T10	1		T26	6		T62	1
all_values[2]	auto[0]	auto[0]	auto[1]	81	1			T6	1		T10	1		T26	2
all_values[2]	auto[0]	auto[1]	auto[0]	124	1			T26	1		T62	2		T34	4
all_values[2]	auto[0]	auto[1]	auto[1]	90	1			T10	1		T26	1		T34	1
all_values[2]	auto[1]	auto[0]	auto[1]	212	1			T6	3		T26	7		T34	4
all_values[2]	auto[1]	auto[1]	auto[1]	166	1			T10	1		T26	1		T62	1
all_values[3]	auto[0]	auto[0]	auto[0]	161	1			T26	4		T62	1		T34	6
all_values[3]	auto[0]	auto[0]	auto[1]	71	1			T26	1		T62	1		T34	1
all_values[3]	auto[0]	auto[1]	auto[0]	164	1			T6	2		T10	2		T26	6
all_values[3]	auto[0]	auto[1]	auto[1]	72	1			T6	1		T26	1		T149	3
all_values[3]	auto[1]	auto[0]	auto[1]	207	1			T26	3		T62	1		T34	1
all_values[3]	auto[1]	auto[1]	auto[1]	165	1			T6	1		T10	2		T26	3
all_values[4]	auto[0]	auto[0]	auto[0]	154	1			T10	2		T26	2		T62	1
all_values[4]	auto[0]	auto[0]	auto[1]	87	1			T6	1		T26	1		T62	2
all_values[4]	auto[0]	auto[1]	auto[0]	141	1			T34	2		T149	9		T150	2
all_values[4]	auto[0]	auto[1]	auto[1]	77	1			T6	1		T26	3		T34	2
all_values[4]	auto[1]	auto[0]	auto[1]	224	1			T6	1		T10	2		T26	5
all_values[4]	auto[1]	auto[1]	auto[1]	157	1			T6	1		T26	7		T62	1
all_values[5]	auto[0]	auto[0]	auto[0]	243	1			T6	2		T10	1		T26	4
all_values[5]	auto[0]	auto[1]	auto[0]	251	1			T6	1		T10	1		T26	5
all_values[5]	auto[1]	auto[0]	auto[1]	176	1			T6	1		T10	1		T26	6
all_values[5]	auto[1]	auto[1]	auto[1]	170	1			T10	1		T26	3		T34	3
all_values[6]	auto[0]	auto[0]	auto[0]	178	1			T10	3		T26	4		T34	3
all_values[6]	auto[0]	auto[0]	auto[1]	75	1			T6	2		T62	1		T34	1
all_values[6]	auto[0]	auto[1]	auto[0]	146	1			T26	3		T34	6		T149	4
all_values[6]	auto[0]	auto[1]	auto[1]	69	1			T26	4		T150	2		T140	1
all_values[6]	auto[1]	auto[0]	auto[1]	210	1			T6	2		T10	1		T26	4
all_values[6]	auto[1]	auto[1]	auto[1]	162	1			T26	3		T62	1		T34	2
all_values[7]	auto[0]	auto[0]	auto[0]	152	1			T26	3		T62	1		T34	4
all_values[7]	auto[0]	auto[0]	auto[1]	83	1			T26	3		T34	1		T149	1
all_values[7]	auto[0]	auto[1]	auto[0]	171	1			T6	2		T10	1		T34	2
all_values[7]	auto[0]	auto[1]	auto[1]	76	1			T6	1		T10	1		T26	2
all_values[7]	auto[1]	auto[0]	auto[1]	199	1			T26	8		T62	1		T34	4
all_values[7]	auto[1]	auto[1]	auto[1]	159	1			T6	1		T10	2		T26	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal