Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2722853	1			T1	14		T2	1382		T4	1
all_values[1]	2722853	1			T1	14		T2	1382		T4	1
all_values[2]	2722853	1			T1	14		T2	1382		T4	1
all_values[3]	2722853	1			T1	14		T2	1382		T4	1
all_values[4]	2722853	1			T1	14		T2	1382		T4	1
all_values[5]	2722853	1			T1	14		T2	1382		T4	1
all_values[6]	2722853	1			T1	14		T2	1382		T4	1
all_values[7]	2722853	1			T1	14		T2	1382		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20462704

1

T1

112

T2

11056

T4

8

auto[1]

1320120

1

T23

28953

T26

31

T30

82

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21760210

1

T1

110

T2

11056

T4

8

auto[1]

22614

1

T1

2

T12

49

T18

200

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2530973	1			T1	14		T2	1382		T4	1
all_values[0]	auto[0]	auto[1]	11196	1			T12	28		T18	73		T23	6
all_values[0]	auto[1]	auto[0]	179673	1			T23	9630		T26	3		T30	4
all_values[0]	auto[1]	auto[1]	1011	1			T23	6		T26	3		T30	5
all_values[1]	auto[0]	auto[0]	2573725	1			T1	14		T2	1382		T4	1
all_values[1]	auto[0]	auto[1]	5527	1			T12	21		T18	71		T23	6
all_values[1]	auto[1]	auto[0]	143175	1			T23	4		T26	1		T30	7
all_values[1]	auto[1]	auto[1]	426	1			T23	6		T30	4		T33	6
all_values[2]	auto[0]	auto[0]	2478268	1			T1	14		T2	1382		T4	1
all_values[2]	auto[0]	auto[1]	2179	1			T18	56		T23	1		T26	44
all_values[2]	auto[1]	auto[0]	242070	1			T23	9633		T30	6		T31	1
all_values[2]	auto[1]	auto[1]	336	1			T23	6		T26	2		T30	4
all_values[3]	auto[0]	auto[0]	2620962	1			T1	14		T2	1382		T4	1
all_values[3]	auto[0]	auto[1]	178	1			T23	6		T26	2		T30	2
all_values[3]	auto[1]	auto[0]	101509	1			T23	2		T30	4		T31	5
all_values[3]	auto[1]	auto[1]	204	1			T23	4		T26	2		T30	5
all_values[4]	auto[0]	auto[0]	2543916	1			T1	14		T2	1382		T4	1
all_values[4]	auto[0]	auto[1]	186	1			T23	3		T30	4		T33	10
all_values[4]	auto[1]	auto[0]	178577	1			T23	4		T26	4		T30	4
all_values[4]	auto[1]	auto[1]	174	1			T23	3		T26	2		T30	7
all_values[5]	auto[0]	auto[0]	2632462	1			T1	12		T2	1382		T4	1
all_values[5]	auto[0]	auto[1]	293	1			T1	2		T23	4		T25	6
all_values[5]	auto[1]	auto[0]	89929	1			T23	9635		T26	2		T30	3
all_values[5]	auto[1]	auto[1]	169	1			T23	4		T30	3		T33	5
all_values[6]	auto[0]	auto[0]	2475684	1			T1	14		T2	1382		T4	1
all_values[6]	auto[0]	auto[1]	186	1			T23	7		T26	1		T30	2
all_values[6]	auto[1]	auto[0]	246798	1			T23	4		T26	3		T30	9
all_values[6]	auto[1]	auto[1]	185	1			T23	5		T26	3		T30	5
all_values[7]	auto[0]	auto[0]	2586771	1			T1	14		T2	1382		T4	1
all_values[7]	auto[0]	auto[1]	198	1			T23	7		T26	1		T30	3
all_values[7]	auto[1]	auto[0]	135718	1			T23	5		T26	5		T30	7
all_values[7]	auto[1]	auto[1]	166	1			T23	2		T26	1		T30	5