Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	32645	1			T2	8		T4	4		T7	2
auto[SpiFlashAddrCfg]	6976	1			T2	6		T4	4		T8	2
auto[SpiFlashAddr3b]	8427	1			T2	4		T4	8		T8	4
auto[SpiFlashAddr4b]	7099	1			T2	2		T4	2		T8	6

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30349

1

T2

20

T4

18

T7

2

auto[1]

24798

1

T12

81

T14

8

T17

145

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29683

1

T2

16

T4

6

T8

8

auto[1]

25464

1

T2

4

T4

12

T7

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	36909	1			T2	8		T7	2		T8	6
values[1]	1018	1			T2	4		T4	4		T12	3
values[2]	1228	1			T2	2		T4	2		T12	8
values[3]	1314	1			T12	5		T14	4		T17	5
values[4]	1378	1			T2	2		T12	6		T17	8
values[5]	1384	1			T8	2		T12	4		T17	4
values[6]	1430	1			T8	2		T17	3		T21	4
values[7]	1374	1			T12	9		T17	11		T21	2
values[8]	9112	1			T2	4		T4	12		T8	6

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31342

1

T2

20

T4

18

T7

2

auto[1]

23805

1

T18

88

T41

1

T26

470

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

53211

1

T2

20

T4

18

T7

2

write

1936

1

T8

2

T12

4

T15

6

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18598

1

T2

8

T4

14

T8

8

valids[0x1]

36549

1

T2

12

T4

4

T7

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1478	1			T8	2		T12	9		T17	2
internal_process_ops[0x5a]	1386	1			T12	5		T17	4		T18	2
internal_process_ops[0x05]	19790	1			T2	2		T7	2		T12	29
internal_process_ops[0x35]	1430	1			T2	4		T12	4		T17	8
internal_process_ops[0x15]	1461	1			T2	2		T12	5		T17	4
internal_process_ops[0x03]	988	1			T12	4		T17	7		T18	2
internal_process_ops[0x0b]	1005	1			T8	2		T12	3		T17	9
internal_process_ops[0x3b]	1033	1			T2	2		T4	2		T8	2
internal_process_ops[0x6b]	1010	1			T12	3		T17	9		T39	4
internal_process_ops[0xbb]	1015	1			T4	2		T8	2		T12	7
internal_process_ops[0xeb]	1007	1			T4	6		T12	6		T14	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

54179

1

T2

20

T4

18

T7

2

auto[1]

968

1

T12

1

T17

7

T18

8

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53240

1

T2

20

T4

18

T7

2

auto[1]

1907

1

T12

5

T15

8

T17

8

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10277

1

T2

8

T4

4

T7

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7493

1

T12

32

T17

89

T21

8

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2134

1

T2

6

T4

4

T8

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1813

1

T12

21

T14

2

T17

15

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2504

1

T2

4

T4

8

T8

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2204

1

T12

17

T14

2

T17

18

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2099

1

T2

2

T4

2

T8

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1833

1

T12

10

T14

4

T17

19

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

70

1

T8

2

T12

1

T15

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

61

1

T17

3

T30

1

T31

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

57

1

T31

3

T35

1

T170

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

60

1

T30

1

T31

1

T34

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

58

1

T12

1

T27

1

T28

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

59

1

T29

1

T30

1

T35

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

50

1

T17

3

T29

1

T34

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

63

1

T12

1

T30

1

T171

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

66

1

T28

1

T31

1

T32

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

43

1

T27

1

T30

5

T31

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

67

1

T28

3

T31

1

T32

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

60

1

T28

1

T30

1

T31

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

72

1

T12

1

T15

4

T17

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

78

1

T17

4

T27

3

T28

5

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

44

1

T17

1

T27

1

T32

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

77

1

T27

1

T28

2

T30

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8167

1

T18

18

T26

164

T44

183

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6213

1

T18

23

T26

99

T44

228

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1278

1

T18

6

T26

28

T44

21

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1305

1

T18

7

T26

25

T44

21

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1585

1

T18

11

T41

1

T26

48

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1658

1

T18

3

T26

46

T44

27

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1341

1

T18

6

T26

23

T44

18

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1307

1

T18

6

T26

15

T44

30

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

53

1

T26

2

T47

5

T172

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

80

1

T18

1

T45

1

T46

6

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

58

1

T44

2

T173

1

T46

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

56

1

T18

3

T44

2

T69

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

46

1

T44

3

T46

4

T172

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

56

1

T18

1

T69

1

T47

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

50

1

T26

1

T44

1

T46

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

64

1

T26

1

T166

2

T47

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

63

1

T44

2

T174

3

T78

6

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

50

1

T44

3

T173

4

T33

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

75

1

T44

1

T33

2

T69

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

52

1

T18

2

T26

5

T47

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

59

1

T26

1

T44

1

T173

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

50

1

T18

1

T26

3

T173

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

80

1

T26

6

T33

1

T175

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

59

1

T26

3

T166

3

T46

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4261	1			T12	27		T15	12		T17	39
auto[0]	values[0]	valids[0x1]	16104	1			T2	8		T7	2		T8	6
auto[0]	values[1]	valids[0x1]	573	1			T2	4		T4	4		T12	3
auto[0]	values[2]	valids[0x0]	505	1			T2	2		T4	2		T12	4
auto[0]	values[2]	valids[0x1]	266	1			T12	4		T17	1		T27	3
auto[0]	values[3]	valids[0x0]	533	1			T12	4		T14	4		T17	3
auto[0]	values[3]	valids[0x1]	294	1			T12	1		T17	2		T93	2
auto[0]	values[4]	valids[0x0]	563	1			T2	2		T12	4		T17	5
auto[0]	values[4]	valids[0x1]	262	1			T12	2		T17	3		T39	2
auto[0]	values[5]	valids[0x0]	500	1			T8	2		T12	1		T39	4
auto[0]	values[5]	valids[0x1]	318	1			T12	3		T17	4		T27	1
auto[0]	values[6]	valids[0x0]	564	1			T17	1		T21	4		T27	3
auto[0]	values[6]	valids[0x1]	258	1			T8	2		T17	2		T93	2
auto[0]	values[7]	valids[0x0]	561	1			T12	4		T17	6		T21	2
auto[0]	values[7]	valids[0x1]	285	1			T12	5		T17	5		T27	1
auto[0]	values[8]	valids[0x0]	3534	1			T2	4		T4	12		T8	6
auto[0]	values[8]	valids[0x1]	1961	1			T12	15		T15	2		T17	20
auto[1]	values[0]	valids[0x0]	3525	1			T18	18		T26	65		T44	57
auto[1]	values[0]	valids[0x1]	13019	1			T18	35		T26	243		T44	387
auto[1]	values[1]	valids[0x1]	445	1			T18	1		T26	22		T44	6
auto[1]	values[2]	valids[0x0]	263	1			T18	2		T26	5		T173	5
auto[1]	values[2]	valids[0x1]	194	1			T18	1		T26	3		T44	1
auto[1]	values[3]	valids[0x0]	287	1			T18	2		T26	5		T44	8
auto[1]	values[3]	valids[0x1]	200	1			T18	2		T26	6		T44	1
auto[1]	values[4]	valids[0x0]	356	1			T18	1		T26	13		T44	2
auto[1]	values[4]	valids[0x1]	197	1			T18	3		T26	4		T44	3
auto[1]	values[5]	valids[0x0]	323	1			T26	13		T44	4		T173	1
auto[1]	values[5]	valids[0x1]	243	1			T18	1		T26	4		T44	9
auto[1]	values[6]	valids[0x0]	387	1			T18	1		T26	11		T44	7
auto[1]	values[6]	valids[0x1]	221	1			T18	2		T26	1		T44	5
auto[1]	values[7]	valids[0x0]	316	1			T18	1		T26	6		T44	2
auto[1]	values[7]	valids[0x1]	212	1			T26	12		T44	2		T33	1
auto[1]	values[8]	valids[0x0]	2120	1			T18	10		T26	30		T44	31
auto[1]	values[8]	valids[0x1]	1497	1			T18	8		T41	1		T26	27