Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3021636

1

T2

5711

T4

1

T7

499

auto[1]

18360

1

T12

19

T15

53

T17

199

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

754172

1

T2

1

T4

1

T7

499

auto[1]

2285824

1

T2

5710

T12

10139

T15

575

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	545111	1			T2	5711		T4	1		T7	3
auto[524288:1048575]	375610	1			T12	264		T17	1940		T18	130
auto[1048576:1572863]	394913	1			T7	496		T12	3068		T17	4512
auto[1572864:2097151]	360683	1			T12	3497		T17	2088		T18	522
auto[2097152:2621439]	370231	1			T12	1638		T17	266		T18	9
auto[2621440:3145727]	316442	1			T12	259		T17	586		T18	2
auto[3145728:3670015]	318512	1			T12	134		T18	647		T39	1
auto[3670016:4194303]	358494	1			T12	1305		T17	516		T18	257

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2307270

1

T2

5711

T4

1

T7

3

auto[1]

732726

1

T7

496

T15

7

T17

2

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2612755

1

T2

5711

T4

1

T7

499

auto[1]

427241

1

T12

12

T17

2881

T18

650

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	152971	1			T2	1		T4	1		T7	3
auto[0]	auto[0]	auto[0:524287]	auto[1]	337198	1			T2	5710		T12	3		T15	530
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	91145	1			T12	7		T17	5		T99	1
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	212061	1			T12	256		T17	1919		T26	3874
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	99072	1			T7	496		T12	5		T17	10
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	231486	1			T12	3052		T17	3812		T26	384
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	91628	1			T12	7		T17	5		T18	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	223406	1			T12	3487		T17	2079		T18	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	86822	1			T12	5		T17	2		T18	5
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	226504	1			T12	1633		T17	261		T18	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	60189	1			T12	2		T17	11		T39	525
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	203684	1			T12	256		T17	435		T26	804
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	86269	1			T18	8		T39	1		T99	46
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	194694	1			T12	133		T18	634		T26	3244
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	76016	1			T12	2		T17	1		T18	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	224964	1			T12	1298		T17	515		T18	256
auto[0]	auto[1]	auto[0:524287]	auto[0]	429	1			T17	1		T99	48		T26	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	51262	1			T17	2226		T27	257		T28	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	356	1			T12	1		T18	2		T26	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	69957	1			T18	128		T26	1870		T27	968
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1932	1			T12	1		T17	5		T99	10
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	60349	1			T12	5		T17	640		T28	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	597	1			T12	1		T17	4		T18	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	43050	1			T12	2		T18	516		T26	768
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	863	1			T17	3		T44	5		T88	234
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	53804	1			T44	3		T173	865		T30	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	2879	1			T12	1		T17	2		T18	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	47549	1			T26	257		T29	2		T32	1415
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	694	1			T12	1		T26	5		T27	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	34609	1			T26	2581		T27	565		T44	2220
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	398	1			T26	5		T27	11		T28	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	54799	1			T26	2790		T27	457		T28	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	280	1			T12	3		T15	8		T26	3
auto[1]	auto[0]	auto[0:524287]	auto[1]	2554	1			T12	6		T15	45		T26	9
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	159	1			T17	1		T26	1		T27	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1268	1			T17	15		T26	34		T27	45
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	186	1			T12	1		T17	2		T44	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1465	1			T12	4		T17	43		T44	13
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	181	1			T18	1		T26	1		T27	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1462	1			T26	3		T27	72		T44	21
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	201	1			T18	2		T26	2		T27	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1574	1			T26	5		T27	45		T44	62
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	170	1			T17	5		T46	4		T69	5
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1375	1			T17	133		T46	6		T69	136
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	207	1			T18	2		T27	1		T44	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1716	1			T18	3		T27	34		T44	73
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	179	1			T12	1		T26	4		T30	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1669	1			T12	4		T26	48		T30	1
auto[1]	auto[1]	auto[0:524287]	auto[0]	47	1			T27	1		T28	1		T32	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	370	1			T27	47		T28	9		T32	6
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	45	1			T27	2		T33	2		T34	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	619	1			T27	5		T34	14		T175	26
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	48	1			T28	1		T30	2		T32	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	375	1			T28	5		T30	5		T32	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	27	1			T166	1		T34	2		T46	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	332	1			T166	4		T34	52		T47	11
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	44	1			T173	1		T30	1		T31	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	419	1			T30	3		T31	1		T46	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	47	1			T26	1		T29	2		T166	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	549	1			T26	4		T29	3		T166	4
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	35	1			T26	2		T44	2		T28	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	288	1			T26	10		T44	92		T29	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	56	1			T26	1		T28	1		T46	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	413	1			T26	2		T28	1		T46	1

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1871394	1			T2	5711		T4	1		T7	3
auto[0]	auto[0]	auto[1]	726715	1			T7	496		T15	3		T17	2
auto[0]	auto[1]	auto[0]	417823	1			T12	12		T17	2881		T18	650
auto[0]	auto[1]	auto[1]	5704	1			T99	48		T27	2		T88	15
auto[1]	auto[0]	auto[0]	14392	1			T12	19		T15	49		T17	199
auto[1]	auto[0]	auto[1]	254	1			T15	4		T26	1		T27	1
auto[1]	auto[1]	auto[0]	3661	1			T26	20		T27	55		T44	92
auto[1]	auto[1]	auto[1]	53	1			T44	2		T166	1		T34	1