Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17521

1

T2

20

T4

18

T7

2

auto[1]

13821

1

T12

81

T14

8

T17

145

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3776	1			T12	40		T17	56		T37	10
values[1]	3778	1			T12	49		T14	8		T17	60
values[2]	3802	1			T17	48		T93	10		T27	127
values[3]	4544	1			T4	18		T7	2		T17	90
values[4]	4250	1			T99	6		T27	31		T28	24
values[5]	3533	1			T2	20		T8	16		T12	40
values[6]	4049	1			T12	20		T38	6		T40	2
values[7]	3610	1			T12	30		T21	20		T27	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4050	1			T12	30		T17	110		T98	6
values[1]	4163	1			T8	16		T38	6		T27	127
values[2]	3108	1			T4	18		T17	104		T40	2
values[3]	4069	1			T7	2		T12	20		T17	20
values[4]	4169	1			T12	65		T17	20		T37	10
values[5]	4004	1			T12	40		T17	125		T39	14
values[6]	3567	1			T2	20		T12	24		T14	8
values[7]	4212	1			T15	79		T17	20		T99	6

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	321	1			T98	6		T170	16		T232	11
auto[0]	values[0]	values[1]	217	1			T30	17		T170	23		T211	25
auto[0]	values[0]	values[2]	330	1			T17	27		T241	2		T242	10
auto[0]	values[0]	values[3]	303	1			T243	12		T170	5		T202	20
auto[0]	values[0]	values[4]	321	1			T12	11		T30	12		T31	12
auto[0]	values[0]	values[5]	191	1			T12	12		T27	19		T244	8
auto[0]	values[0]	values[6]	181	1			T27	9		T29	10		T245	4
auto[0]	values[0]	values[7]	183	1			T17	16		T170	9		T212	11
auto[0]	values[1]	values[0]	217	1			T30	11		T77	14		T175	26
auto[0]	values[1]	values[1]	405	1			T31	37		T35	26		T46	17
auto[0]	values[1]	values[2]	222	1			T17	13		T211	12		T230	13
auto[0]	values[1]	values[3]	257	1			T17	14		T246	4		T171	13
auto[0]	values[1]	values[4]	324	1			T12	12		T17	13		T27	11
auto[0]	values[1]	values[5]	204	1			T30	11		T167	10		T175	11
auto[0]	values[1]	values[6]	264	1			T12	8		T32	11		T35	13
auto[0]	values[1]	values[7]	232	1			T30	13		T231	12		T228	15
auto[0]	values[2]	values[0]	225	1			T47	7		T247	20		T230	11
auto[0]	values[2]	values[1]	490	1			T27	16		T56	85		T195	10
auto[0]	values[2]	values[2]	289	1			T17	41		T163	2		T170	11
auto[0]	values[2]	values[3]	296	1			T188	105		T230	30		T208	16
auto[0]	values[2]	values[4]	238	1			T93	10		T171	20		T170	11
auto[0]	values[2]	values[5]	151	1			T31	9		T46	15		T170	9
auto[0]	values[2]	values[6]	210	1			T196	10		T203	22		T170	13
auto[0]	values[2]	values[7]	277	1			T30	15		T248	6		T46	11
auto[0]	values[3]	values[0]	473	1			T17	12		T30	14		T31	9
auto[0]	values[3]	values[1]	357	1			T28	24		T30	23		T188	15
auto[0]	values[3]	values[2]	180	1			T4	18		T30	8		T171	9
auto[0]	values[3]	values[3]	414	1			T7	2		T29	13		T30	7
auto[0]	values[3]	values[4]	373	1			T46	10		T170	27		T249	22
auto[0]	values[3]	values[5]	342	1			T17	10		T39	14		T30	13
auto[0]	values[3]	values[6]	361	1			T171	5		T250	4		T212	116
auto[0]	values[3]	values[7]	319	1			T30	26		T46	15		T170	68
auto[0]	values[4]	values[0]	288	1			T32	15		T188	31		T80	14
auto[0]	values[4]	values[1]	313	1			T251	14		T34	4		T35	19
auto[0]	values[4]	values[2]	198	1			T46	11		T175	15		T211	13
auto[0]	values[4]	values[3]	251	1			T31	15		T170	10		T229	45
auto[0]	values[4]	values[4]	231	1			T28	14		T32	13		T171	33
auto[0]	values[4]	values[5]	206	1			T252	6		T31	11		T47	16
auto[0]	values[4]	values[6]	348	1			T30	10		T171	15		T55	46
auto[0]	values[4]	values[7]	453	1			T99	6		T27	12		T49	8
auto[0]	values[5]	values[0]	231	1			T17	11		T30	15		T31	19
auto[0]	values[5]	values[1]	176	1			T8	16		T171	12		T47	13
auto[0]	values[5]	values[2]	236	1			T171	9		T47	9		T229	20
auto[0]	values[5]	values[3]	283	1			T12	11		T210	10		T211	19
auto[0]	values[5]	values[4]	213	1			T12	10		T31	16		T35	24
auto[0]	values[5]	values[5]	308	1			T17	97		T30	13		T46	23
auto[0]	values[5]	values[6]	153	1			T2	20		T33	14		T35	12
auto[0]	values[5]	values[7]	387	1			T15	79		T27	7		T35	11
auto[0]	values[6]	values[0]	262	1			T214	8		T188	10		T157	15
auto[0]	values[6]	values[1]	224	1			T175	10		T211	8		T157	9
auto[0]	values[6]	values[2]	222	1			T40	2		T88	24		T170	12
auto[0]	values[6]	values[3]	351	1			T46	16		T72	18		T175	13
auto[0]	values[6]	values[4]	267	1			T253	2		T206	10		T170	12
auto[0]	values[6]	values[5]	300	1			T12	10		T171	11		T35	8
auto[0]	values[6]	values[6]	259	1			T27	48		T32	16		T215	13
auto[0]	values[6]	values[7]	307	1			T100	18		T171	8		T33	17
auto[0]	values[7]	values[0]	374	1			T12	24		T27	11		T170	110
auto[0]	values[7]	values[1]	170	1			T28	15		T240	14		T170	12
auto[0]	values[7]	values[2]	145	1			T254	12		T255	24		T256	4
auto[0]	values[7]	values[3]	324	1			T31	13		T90	28		T79	11
auto[0]	values[7]	values[4]	267	1			T28	11		T30	10		T34	13
auto[0]	values[7]	values[5]	318	1			T171	11		T34	9		T223	18
auto[0]	values[7]	values[6]	111	1			T157	17		T228	22		T207	19
auto[0]	values[7]	values[7]	178	1			T28	9		T47	22		T157	10
auto[1]	values[0]	values[0]	109	1			T170	4		T232	9		T215	13
auto[1]	values[0]	values[1]	108	1			T30	3		T170	5		T211	21
auto[1]	values[0]	values[2]	201	1			T17	9		T32	9		T175	6
auto[1]	values[0]	values[3]	149	1			T170	15		T187	12		T158	5
auto[1]	values[0]	values[4]	243	1			T12	9		T37	10		T30	10
auto[1]	values[0]	values[5]	259	1			T12	8		T27	69		T197	10
auto[1]	values[0]	values[6]	334	1			T27	95		T29	12		T46	13
auto[1]	values[0]	values[7]	326	1			T17	4		T170	33		T212	9
auto[1]	values[1]	values[0]	168	1			T30	11		T175	21		T227	18
auto[1]	values[1]	values[1]	286	1			T31	17		T35	19		T46	8
auto[1]	values[1]	values[2]	64	1			T17	7		T211	8		T230	7
auto[1]	values[1]	values[3]	112	1			T17	6		T171	7		T170	7
auto[1]	values[1]	values[4]	331	1			T12	13		T17	7		T27	9
auto[1]	values[1]	values[5]	186	1			T30	9		T175	12		T257	9
auto[1]	values[1]	values[6]	309	1			T12	16		T14	8		T32	9
auto[1]	values[1]	values[7]	197	1			T30	7		T228	5		T207	6
auto[1]	values[2]	values[0]	167	1			T47	14		T230	9		T191	8
auto[1]	values[2]	values[1]	273	1			T27	111		T30	11		T170	17
auto[1]	values[2]	values[2]	370	1			T17	7		T170	9		T211	11
auto[1]	values[2]	values[3]	141	1			T188	18		T230	31		T208	4
auto[1]	values[2]	values[4]	201	1			T171	8		T170	9		T214	7
auto[1]	values[2]	values[5]	230	1			T31	19		T46	5		T170	65
auto[1]	values[2]	values[6]	128	1			T170	37		T214	4		T187	5
auto[1]	values[2]	values[7]	116	1			T30	5		T258	10		T46	11
auto[1]	values[3]	values[0]	262	1			T17	58		T30	6		T31	11
auto[1]	values[3]	values[1]	193	1			T28	8		T30	45		T188	6
auto[1]	values[3]	values[2]	156	1			T30	12		T171	23		T175	8
auto[1]	values[3]	values[3]	243	1			T29	40		T30	13		T35	50
auto[1]	values[3]	values[4]	267	1			T46	10		T170	12		T79	7
auto[1]	values[3]	values[5]	192	1			T17	10		T30	8		T170	12
auto[1]	values[3]	values[6]	170	1			T171	20		T212	8		T129	8
auto[1]	values[3]	values[7]	242	1			T30	4		T46	10		T170	9
auto[1]	values[4]	values[0]	257	1			T32	7		T188	11		T80	25
auto[1]	values[4]	values[1]	301	1			T34	27		T35	10		T47	14
auto[1]	values[4]	values[2]	178	1			T46	13		T73	2		T175	5
auto[1]	values[4]	values[3]	224	1			T31	5		T170	10		T229	16
auto[1]	values[4]	values[4]	134	1			T28	10		T32	12		T171	21
auto[1]	values[4]	values[5]	224	1			T31	11		T47	7		T159	9
auto[1]	values[4]	values[6]	342	1			T30	10		T171	5		T46	9
auto[1]	values[4]	values[7]	302	1			T27	19		T34	12		T170	7
auto[1]	values[5]	values[0]	180	1			T17	29		T30	6		T31	27
auto[1]	values[5]	values[1]	148	1			T171	24		T47	7		T211	14
auto[1]	values[5]	values[2]	82	1			T171	11		T47	14		T229	3
auto[1]	values[5]	values[3]	182	1			T12	9		T211	11		T214	8
auto[1]	values[5]	values[4]	301	1			T12	10		T31	7		T35	16
auto[1]	values[5]	values[5]	144	1			T17	8		T30	7		T46	17
auto[1]	values[5]	values[6]	140	1			T33	7		T35	8		T79	12
auto[1]	values[5]	values[7]	369	1			T27	39		T35	14		T170	5
auto[1]	values[6]	values[0]	261	1			T214	12		T188	10		T157	5
auto[1]	values[6]	values[1]	259	1			T38	6		T175	10		T211	12
auto[1]	values[6]	values[2]	152	1			T170	14		T212	7		T229	27
auto[1]	values[6]	values[3]	229	1			T46	25		T175	15		T47	6
auto[1]	values[6]	values[4]	256	1			T170	48		T232	9		T80	15
auto[1]	values[6]	values[5]	385	1			T12	10		T171	9		T35	12
auto[1]	values[6]	values[6]	157	1			T27	9		T32	11		T259	4
auto[1]	values[6]	values[7]	158	1			T171	12		T33	6		T214	11
auto[1]	values[7]	values[0]	255	1			T12	6		T27	9		T170	30
auto[1]	values[7]	values[1]	243	1			T28	12		T240	38		T170	8
auto[1]	values[7]	values[2]	83	1			T255	8		T22	18		T260	10
auto[1]	values[7]	values[3]	310	1			T21	20		T31	7		T79	12
auto[1]	values[7]	values[4]	202	1			T28	9		T30	14		T34	7
auto[1]	values[7]	values[5]	364	1			T194	20		T171	9		T34	11
auto[1]	values[7]	values[6]	100	1			T157	5		T228	30		T207	7
auto[1]	values[7]	values[7]	166	1			T28	25		T47	5		T157	14