Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	357	1			T12	2		T17	3		T27	4
auto[ReadAddrCrossIntoMailbox]	263	1			T12	3		T17	1		T27	5
auto[ReadAddrCrossOutOfMailbox]	325	1			T12	1		T17	3		T27	2
auto[ReadAddrCrossAllMailbox]	212	1			T12	2		T17	2		T27	2
auto[ReadAddrOutsideMailbox]	3546	1			T2	2		T4	10		T8	6

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2359

1

T2

1

T4

5

T8

3

auto[1]

2344

1

T2

1

T4

5

T8

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	782	1			T12	4		T17	7		T39	2
read_ops[0x0b]	764	1			T8	2		T12	3		T17	9
read_ops[0x3b]	795	1			T2	2		T4	2		T8	2
read_ops[0x6b]	804	1			T12	3		T17	9		T39	4
read_ops[0xbb]	782	1			T4	2		T8	2		T12	7
read_ops[0xeb]	776	1			T4	6		T12	6		T14	4

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	18	1			T171	1		T175	1		T170	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T27	1		T31	2		T34	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T171	2		T47	2		T170	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	17	1			T30	1		T170	1		T211	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T17	1		T30	1		T171	3
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T12	1		T31	1		T35	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T17	1		T46	1		T175	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	10	1			T170	1		T238	1		T22	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	325	1			T12	3		T17	1		T39	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	293	1			T17	4		T39	1		T27	5
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T17	1		T27	1		T29	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T30	1		T171	1		T79	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T28	1		T31	2		T46	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T12	1		T30	2		T33	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T27	1		T31	1		T34	3
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T33	1		T212	1		T215	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T27	1		T31	1		T32	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T33	1		T34	1		T46	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	245	1			T8	1		T12	2		T17	5
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	305	1			T8	1		T17	3		T39	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T17	1		T195	1		T167	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T195	1		T30	1		T167	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T17	1		T27	1		T34	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T12	2		T34	1		T261	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T28	1		T32	1		T167	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T31	1		T167	1		T171	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	25	1			T12	1		T17	1		T28	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T167	1		T261	1		T92	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	302	1			T2	1		T4	1		T8	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	292	1			T2	1		T4	1		T8	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T12	1		T17	1		T31	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T246	2		T171	1		T46	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T31	1		T47	1		T211	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T31	1		T32	1		T34	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T17	2		T171	1		T35	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T32	1		T34	2		T46	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T12	1		T47	1		T188	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T30	1		T32	1		T171	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	304	1			T12	1		T17	5		T39	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	296	1			T17	1		T39	2		T100	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T12	1		T196	1		T47	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	22	1			T27	2		T196	1		T171	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T31	1		T35	1		T46	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T27	3		T30	1		T31	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	35	1			T28	1		T31	1		T34	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T32	1		T34	1		T257	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T32	1		T47	2		T211	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T30	1		T47	1		T228	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	287	1			T4	1		T8	1		T17	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	295	1			T4	1		T8	1		T12	6
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T31	1		T33	1		T35	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T30	1		T175	3		T47	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T27	1		T32	1		T171	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T46	2		T170	1		T229	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T28	1		T33	1		T34	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T27	1		T171	1		T47	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T238	1		T262	1		T129	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T27	1		T32	1		T79	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	303	1			T4	3		T12	3		T14	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	299	1			T4	3		T12	3		T14	2