Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2722853	1			T1	14		T2	1382		T4	1
all_pins[1]	2722853	1			T1	14		T2	1382		T4	1
all_pins[2]	2722853	1			T1	14		T2	1382		T4	1
all_pins[3]	2722853	1			T1	14		T2	1382		T4	1
all_pins[4]	2722853	1			T1	14		T2	1382		T4	1
all_pins[5]	2722853	1			T1	14		T2	1382		T4	1
all_pins[6]	2722853	1			T1	14		T2	1382		T4	1
all_pins[7]	2722853	1			T1	14		T2	1382		T4	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21531680	1			T1	112		T2	11056		T4	8
values[0x1]	251144	1			T23	436		T26	13		T30	38
transitions[0x0=>0x1]	249434	1			T23	427		T26	10		T30	27
transitions[0x1=>0x0]	249441	1			T23	427		T26	10		T30	27

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2721766	1			T1	14		T2	1382		T4	1
all_pins[0]	values[0x1]	1087	1			T23	6		T26	3		T30	5
all_pins[0]	transitions[0x0=>0x1]	797	1			T23	3		T26	3		T30	3
all_pins[0]	transitions[0x1=>0x0]	159	1			T23	3		T30	2		T33	6
all_pins[1]	values[0x0]	2722404	1			T1	14		T2	1382		T4	1
all_pins[1]	values[0x1]	449	1			T23	6		T30	4		T33	6
all_pins[1]	transitions[0x0=>0x1]	326	1			T23	5		T30	3		T33	3
all_pins[1]	transitions[0x1=>0x0]	222	1			T23	5		T26	2		T30	3
all_pins[2]	values[0x0]	2722508	1			T1	14		T2	1382		T4	1
all_pins[2]	values[0x1]	345	1			T23	6		T26	2		T30	4
all_pins[2]	transitions[0x0=>0x1]	302	1			T23	5		T30	4		T31	3
all_pins[2]	transitions[0x1=>0x0]	161	1			T23	3		T30	5		T31	2
all_pins[3]	values[0x0]	2722649	1			T1	14		T2	1382		T4	1
all_pins[3]	values[0x1]	204	1			T23	4		T26	2		T30	5
all_pins[3]	transitions[0x0=>0x1]	159	1			T23	3		T26	2		T30	2
all_pins[3]	transitions[0x1=>0x0]	129	1			T23	2		T26	2		T30	4
all_pins[4]	values[0x0]	2722679	1			T1	14		T2	1382		T4	1
all_pins[4]	values[0x1]	174	1			T23	3		T26	2		T30	7
all_pins[4]	transitions[0x0=>0x1]	135	1			T23	1		T26	2		T30	7
all_pins[4]	transitions[0x1=>0x0]	2226	1			T23	402		T30	3		T33	179
all_pins[5]	values[0x0]	2720588	1			T1	14		T2	1382		T4	1
all_pins[5]	values[0x1]	2265	1			T23	404		T30	3		T33	180
all_pins[5]	transitions[0x0=>0x1]	1173	1			T23	403		T30	1		T33	179
all_pins[5]	transitions[0x1=>0x0]	245362	1			T23	4		T26	3		T30	3
all_pins[6]	values[0x0]	2476399	1			T1	14		T2	1382		T4	1
all_pins[6]	values[0x1]	246454	1			T23	5		T26	3		T30	5
all_pins[6]	transitions[0x0=>0x1]	246415	1			T23	5		T26	2		T30	4
all_pins[6]	transitions[0x1=>0x0]	127	1			T23	2		T30	4		T31	1
all_pins[7]	values[0x0]	2722687	1			T1	14		T2	1382		T4	1
all_pins[7]	values[0x1]	166	1			T23	2		T26	1		T30	5
all_pins[7]	transitions[0x0=>0x1]	127	1			T23	2		T26	1		T30	3
all_pins[7]	transitions[0x1=>0x0]	1055	1			T23	6		T26	3		T30	3