Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4030	1			T12	20		T93	10		T27	88
values[1]	3699	1			T15	79		T17	48		T27	20
values[2]	3472	1			T2	20		T12	20		T17	20
values[3]	4014	1			T12	20		T14	8		T17	165
values[4]	3995	1			T12	25		T17	20		T99	6
values[5]	4202	1			T7	2		T8	16		T12	54
values[6]	4059	1			T4	18		T17	20		T38	6
values[7]	3871	1			T12	40		T17	90		T27	102

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4544	1			T12	45		T17	68		T37	10
values[1]	3640	1			T12	50		T15	79		T17	20
values[2]	3737	1			T12	20		T17	76		T98	6
values[3]	4162	1			T12	20		T27	57		T210	10
values[4]	4166	1			T2	20		T12	24		T17	20
values[5]	3705	1			T12	20		T38	6		T27	45
values[6]	3370	1			T4	18		T7	2		T8	16
values[7]	4018	1			T14	8		T17	70		T93	10

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30841

1

T2

20

T4

18

T7

2

auto[1]

501

1

T12

1

T17

7

T27

5

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	746	1			T12	20		T55	46		T228	41
auto[0]	values[0]	values[1]	600	1			T27	88		T28	26		T171	20
auto[0]	values[0]	values[2]	158	1			T212	20		T219	4		T207	18
auto[0]	values[0]	values[3]	311	1			T30	19		T194	20		T46	25
auto[0]	values[0]	values[4]	522	1			T171	34		T35	20		T90	28
auto[0]	values[0]	values[5]	708	1			T35	23		T170	115		T211	40
auto[0]	values[0]	values[6]	447	1			T171	32		T35	40		T250	4
auto[0]	values[0]	values[7]	489	1			T93	10		T28	34		T77	14
auto[0]	values[1]	values[0]	544	1			T17	45		T28	27		T196	10
auto[0]	values[1]	values[1]	517	1			T15	79		T46	21		T170	28
auto[0]	values[1]	values[2]	656	1			T30	21		T33	20		T263	10
auto[0]	values[1]	values[3]	605	1			T30	20		T31	20		T212	85
auto[0]	values[1]	values[4]	417	1			T32	23		T35	52		T188	20
auto[0]	values[1]	values[5]	322	1			T27	20		T35	25		T170	18
auto[0]	values[1]	values[6]	223	1			T29	52		T32	20		T73	2
auto[0]	values[1]	values[7]	349	1			T171	20		T211	46		T190	20
auto[0]	values[2]	values[0]	552	1			T40	2		T170	83		T216	75
auto[0]	values[2]	values[1]	423	1			T28	22		T35	23		T89	24
auto[0]	values[2]	values[2]	396	1			T31	20		T171	25		T35	20
auto[0]	values[2]	values[3]	518	1			T31	19		T34	31		T46	22
auto[0]	values[2]	values[4]	553	1			T2	20		T30	20		T170	50
auto[0]	values[2]	values[5]	254	1			T12	20		T31	22		T211	20
auto[0]	values[2]	values[6]	191	1			T17	20		T79	20		T232	20
auto[0]	values[2]	values[7]	535	1			T30	39		T46	20		T227	18
auto[0]	values[3]	values[0]	346	1			T30	20		T175	27		T238	30
auto[0]	values[3]	values[1]	306	1			T12	20		T258	10		T170	20
auto[0]	values[3]	values[2]	775	1			T17	38		T98	6		T30	18
auto[0]	values[3]	values[3]	416	1			T34	64		T170	20		T79	23
auto[0]	values[3]	values[4]	546	1			T21	20		T27	46		T30	47
auto[0]	values[3]	values[5]	292	1			T47	48		T264	4		T193	34
auto[0]	values[3]	values[6]	580	1			T17	124		T197	10		T30	24
auto[0]	values[3]	values[7]	697	1			T14	8		T100	18		T31	20
auto[0]	values[4]	values[0]	546	1			T12	25		T99	6		T32	27
auto[0]	values[4]	values[1]	537	1			T17	20		T88	24		T30	20
auto[0]	values[4]	values[2]	538	1			T27	102		T31	20		T265	6
auto[0]	values[4]	values[3]	344	1			T27	56		T210	10		T251	14
auto[0]	values[4]	values[4]	523	1			T31	21		T243	12		T266	2
auto[0]	values[4]	values[5]	664	1			T171	36		T34	20		T175	20
auto[0]	values[4]	values[6]	509	1			T30	21		T225	8		T212	144
auto[0]	values[4]	values[7]	279	1			T175	20		T80	22		T267	2
auto[0]	values[5]	values[0]	602	1			T37	10		T56	85		T30	20
auto[0]	values[5]	values[1]	360	1			T12	30		T167	10		T34	26
auto[0]	values[5]	values[2]	394	1			T17	36		T253	2		T268	4
auto[0]	values[5]	values[3]	669	1			T30	20		T31	26		T33	22
auto[0]	values[5]	values[4]	382	1			T12	23		T248	6		T171	20
auto[0]	values[5]	values[5]	637	1			T27	25		T170	53		T211	22
auto[0]	values[5]	values[6]	498	1			T7	2		T8	16		T170	20
auto[0]	values[5]	values[7]	582	1			T195	10		T30	21		T170	40
auto[0]	values[6]	values[0]	680	1			T17	20		T30	19		T32	24
auto[0]	values[6]	values[1]	490	1			T39	14		T46	20		T170	58
auto[0]	values[6]	values[2]	305	1			T241	2		T240	52		T228	19
auto[0]	values[6]	values[3]	639	1			T31	23		T72	18		T175	20
auto[0]	values[6]	values[4]	516	1			T46	20		T175	20		T79	20
auto[0]	values[6]	values[5]	431	1			T38	6		T171	18		T170	22
auto[0]	values[6]	values[6]	349	1			T4	18		T27	19		T171	20
auto[0]	values[6]	values[7]	570	1			T27	31		T242	10		T30	18
auto[0]	values[7]	values[0]	439	1			T31	34		T79	20		T269	19
auto[0]	values[7]	values[1]	358	1			T46	25		T216	20		T214	20
auto[0]	values[7]	values[2]	454	1			T12	20		T47	21		T215	22
auto[0]	values[7]	values[3]	585	1			T12	20		T35	29		T46	40
auto[0]	values[7]	values[4]	648	1			T17	20		T27	101		T28	20
auto[0]	values[7]	values[5]	343	1			T244	8		T270	72		T256	4
auto[0]	values[7]	values[6]	524	1			T29	22		T246	4		T171	20
auto[0]	values[7]	values[7]	452	1			T17	69		T30	28		T211	28
auto[1]	values[0]	values[0]	12	1			T228	3		T271	4		T129	1
auto[1]	values[0]	values[1]	3	1			T28	1		T170	1		T272	1
auto[1]	values[0]	values[2]	7	1			T207	2		T273	2		T274	3
auto[1]	values[0]	values[3]	4	1			T30	1		T190	2		T191	1
auto[1]	values[0]	values[4]	6	1			T47	2		T211	1		T207	2
auto[1]	values[0]	values[5]	8	1			T35	2		T170	1		T211	1
auto[1]	values[0]	values[6]	7	1			T170	3		T159	2		T275	1
auto[1]	values[0]	values[7]	2	1			T212	1		T276	1		-	-
auto[1]	values[1]	values[0]	21	1			T17	3		T28	5		T47	3
auto[1]	values[1]	values[1]	7	1			T46	3		T208	1		T277	1
auto[1]	values[1]	values[2]	9	1			T228	1		T205	1		T278	1
auto[1]	values[1]	values[3]	9	1			T212	2		T279	2		T278	2
auto[1]	values[1]	values[4]	4	1			T280	1		T221	2		T260	1
auto[1]	values[1]	values[5]	6	1			T170	2		T212	2		T281	1
auto[1]	values[1]	values[6]	5	1			T29	1		T128	2		T282	2
auto[1]	values[1]	values[7]	5	1			T190	1		T272	1		T283	1
auto[1]	values[2]	values[0]	8	1			T170	1		T80	2		T284	3
auto[1]	values[2]	values[1]	8	1			T28	2		T272	1		T283	2
auto[1]	values[2]	values[2]	2	1			T188	1		T284	1		-	-
auto[1]	values[2]	values[3]	12	1			T31	1		T207	1		T161	4
auto[1]	values[2]	values[4]	7	1			T79	1		T187	1		T285	2
auto[1]	values[2]	values[5]	5	1			T31	1		T286	1		T287	3
auto[1]	values[2]	values[6]	3	1			T187	2		T278	1		-	-
auto[1]	values[2]	values[7]	5	1			T30	1		T46	2		T257	1
auto[1]	values[3]	values[0]	4	1			T128	3		T235	1		-	-
auto[1]	values[3]	values[1]	3	1			T288	2		T289	1		-	-
auto[1]	values[3]	values[2]	12	1			T17	2		T30	2		T290	2
auto[1]	values[3]	values[3]	8	1			T170	4		T79	1		T207	1
auto[1]	values[3]	values[4]	13	1			T30	1		T79	3		T215	3
auto[1]	values[3]	values[5]	3	1			T289	3		-	-		-	-
auto[1]	values[3]	values[6]	4	1			T17	1		T205	1		T236	1
auto[1]	values[3]	values[7]	9	1			T32	2		T47	1		T80	2
auto[1]	values[4]	values[0]	7	1			T208	1		T128	2		T291	1
auto[1]	values[4]	values[1]	11	1			T191	2		T279	1		T161	2
auto[1]	values[4]	values[2]	8	1			T27	2		T192	1		T161	1
auto[1]	values[4]	values[3]	3	1			T27	1		T187	2		-	-
auto[1]	values[4]	values[4]	8	1			T79	2		T262	4		T273	2
auto[1]	values[4]	values[5]	7	1			T214	2		T229	3		T292	1
auto[1]	values[4]	values[6]	4	1			T188	1		T293	2		T294	1
auto[1]	values[4]	values[7]	7	1			T295	1		T289	6		-	-
auto[1]	values[5]	values[0]	7	1			T171	1		T35	1		T128	2
auto[1]	values[5]	values[1]	5	1			T34	1		T80	2		T280	2
auto[1]	values[5]	values[2]	10	1			T207	4		T192	1		T288	1
auto[1]	values[5]	values[3]	10	1			T33	1		T34	2		T188	4
auto[1]	values[5]	values[4]	3	1			T12	1		T161	1		T275	1
auto[1]	values[5]	values[5]	16	1			T211	2		T190	2		T279	2
auto[1]	values[5]	values[6]	13	1			T170	1		T212	2		T207	3
auto[1]	values[5]	values[7]	14	1			T30	1		T221	2		T272	1
auto[1]	values[6]	values[0]	18	1			T30	3		T32	1		T211	2
auto[1]	values[6]	values[1]	8	1			T170	1		T230	2		T287	3
auto[1]	values[6]	values[2]	3	1			T228	1		T207	1		T161	1
auto[1]	values[6]	values[3]	14	1			T31	5		T214	3		T290	3
auto[1]	values[6]	values[4]	13	1			T229	2		T207	4		T296	4
auto[1]	values[6]	values[5]	5	1			T171	2		T80	1		T286	2
auto[1]	values[6]	values[6]	8	1			T27	1		T170	2		T80	1
auto[1]	values[6]	values[7]	10	1			T30	2		T31	1		T161	2
auto[1]	values[7]	values[0]	12	1			T79	1		T269	2		T187	2
auto[1]	values[7]	values[1]	4	1			T157	2		T161	1		T297	1
auto[1]	values[7]	values[2]	10	1			T47	1		T295	4		T276	4
auto[1]	values[7]	values[3]	15	1			T212	5		T276	5		T277	3
auto[1]	values[7]	values[4]	5	1			T27	1		T46	2		T215	2
auto[1]	values[7]	values[5]	4	1			T22	1		T260	3		-	-
auto[1]	values[7]	values[6]	5	1			T298	1		T260	4		-	-
auto[1]	values[7]	values[7]	13	1			T17	1		T30	2		T211	1