Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1798

1

T1

1

T6

8

T12

6

auto[1]

1781

1

T6

6

T11

3

T12

5

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1910

1

T1

1

T6

14

T12

11

auto[1]

1669

1

T11

3

T16

34

T20

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2861

1

T1

1

T6

8

T11

3

auto[1]

718

1

T6

6

T12

1

T18

7

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	724	1			T6	4		T11	1		T16	5
valid[1]	708	1			T6	1		T11	1		T12	2
valid[2]	753	1			T1	1		T6	2		T12	4
valid[3]	683	1			T6	5		T11	1		T12	2
valid[4]	711	1			T6	2		T12	3		T16	7

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	123	1			T6	2		T18	1		T23	2
auto[0]	auto[0]	valid[0]	auto[1]	171	1			T16	2		T24	1		T26	1
auto[0]	auto[0]	valid[1]	auto[0]	110	1			T6	1		T12	1		T18	2
auto[0]	auto[0]	valid[1]	auto[1]	172	1			T16	6		T20	1		T87	1
auto[0]	auto[0]	valid[2]	auto[0]	138	1			T1	1		T12	3		T18	2
auto[0]	auto[0]	valid[2]	auto[1]	180	1			T16	3		T87	1		T30	2
auto[0]	auto[0]	valid[3]	auto[0]	105	1			T6	2		T18	1		T23	2
auto[0]	auto[0]	valid[3]	auto[1]	178	1			T16	3		T314	1		T30	1
auto[0]	auto[0]	valid[4]	auto[0]	111	1			T12	1		T18	3		T26	1
auto[0]	auto[0]	valid[4]	auto[1]	162	1			T16	6		T315	4		T32	1
auto[0]	auto[1]	valid[0]	auto[0]	116	1			T6	1		T18	2		T23	2
auto[0]	auto[1]	valid[0]	auto[1]	166	1			T11	1		T16	3		T20	1
auto[0]	auto[1]	valid[1]	auto[0]	120	1			T12	1		T18	1		T28	1
auto[0]	auto[1]	valid[1]	auto[1]	159	1			T11	1		T16	2		T314	2
auto[0]	auto[1]	valid[2]	auto[0]	118	1			T6	1		T18	1		T23	2
auto[0]	auto[1]	valid[2]	auto[1]	175	1			T16	4		T20	2		T45	1
auto[0]	auto[1]	valid[3]	auto[0]	112	1			T6	1		T12	2		T18	3
auto[0]	auto[1]	valid[3]	auto[1]	149	1			T11	1		T16	4		T20	1
auto[0]	auto[1]	valid[4]	auto[0]	139	1			T12	2		T18	3		T26	1
auto[0]	auto[1]	valid[4]	auto[1]	157	1			T16	1		T45	2		T87	1
auto[1]	auto[0]	valid[0]	auto[0]	74	1			T6	1		T24	1		T26	1
auto[1]	auto[0]	valid[1]	auto[0]	65	1			T45	1		T173	1		T166	2
auto[1]	auto[0]	valid[2]	auto[0]	76	1			T6	1		T12	1		T18	1
auto[1]	auto[0]	valid[3]	auto[0]	68	1			T18	1		T26	1		T173	1
auto[1]	auto[0]	valid[4]	auto[0]	65	1			T6	1		T23	1		T45	1
auto[1]	auto[1]	valid[0]	auto[0]	74	1			T18	1		T23	2		T26	1
auto[1]	auto[1]	valid[1]	auto[0]	82	1			T18	1		T45	1		T30	2
auto[1]	auto[1]	valid[2]	auto[0]	66	1			T18	1		T23	2		T30	1
auto[1]	auto[1]	valid[3]	auto[0]	71	1			T6	2		T18	1		T23	1
auto[1]	auto[1]	valid[4]	auto[0]	77	1			T6	1		T18	1		T173	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal