Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49772

1

T1

4

T6

407

T12

305

auto[1]

17232

1

T9

35

T11

3

T16

457

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48693

1

T1

3

T6

276

T9

35

auto[1]

18311

1

T1

1

T6

131

T12

88

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34570	1			T1	4		T6	205		T9	19
others[1]	5661	1			T6	30		T9	6		T12	28
others[2]	5648	1			T6	42		T9	1		T12	19
others[3]	6340	1			T6	43		T9	5		T12	30
interest[1]	3653	1			T6	10		T9	3		T12	16
interest[4]	22467	1			T1	3		T6	134		T9	14
interest[64]	11132	1			T6	77		T9	1		T12	51

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16086	1			T1	3		T6	146		T12	118
auto[0]	auto[0]	others[1]	2688	1			T6	20		T12	19		T18	26
auto[0]	auto[0]	others[2]	2753	1			T6	30		T12	11		T18	38
auto[0]	auto[0]	others[3]	2939	1			T6	28		T12	19		T18	36
auto[0]	auto[0]	interest[1]	1738	1			T6	7		T12	12		T18	15
auto[0]	auto[0]	interest[4]	10375	1			T1	2		T6	97		T12	82
auto[0]	auto[0]	interest[64]	5257	1			T6	45		T12	38		T18	67
auto[0]	auto[1]	others[0]	9041	1			T9	19		T11	3		T16	233
auto[0]	auto[1]	others[1]	1435	1			T9	6		T16	29		T20	6
auto[0]	auto[1]	others[2]	1370	1			T9	1		T16	42		T20	3
auto[0]	auto[1]	others[3]	1607	1			T9	5		T16	56		T20	8
auto[0]	auto[1]	interest[1]	916	1			T9	3		T16	28		T20	2
auto[0]	auto[1]	interest[4]	6020	1			T9	14		T11	3		T16	166
auto[0]	auto[1]	interest[64]	2863	1			T9	1		T16	69		T20	20
auto[1]	auto[0]	others[0]	9443	1			T1	1		T6	59		T12	43
auto[1]	auto[0]	others[1]	1538	1			T6	10		T12	9		T18	7
auto[1]	auto[0]	others[2]	1525	1			T6	12		T12	8		T18	11
auto[1]	auto[0]	others[3]	1794	1			T6	15		T12	11		T18	16
auto[1]	auto[0]	interest[1]	999	1			T6	3		T12	4		T18	8
auto[1]	auto[0]	interest[4]	6072	1			T1	1		T6	37		T12	28
auto[1]	auto[0]	interest[64]	3012	1			T6	32		T12	13		T18	25

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal