Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	781	1			T23	20		T26	4		T30	18
all_values[1]	781	1			T23	20		T26	4		T30	18
all_values[2]	781	1			T23	20		T26	4		T30	18
all_values[3]	781	1			T23	20		T26	4		T30	18
all_values[4]	781	1			T23	20		T26	4		T30	18
all_values[5]	781	1			T23	20		T26	4		T30	18
all_values[6]	781	1			T23	20		T26	4		T30	18
all_values[7]	781	1			T23	20		T26	4		T30	18

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3372

1

T23

82

T26

17

T30

81

auto[1]

2876

1

T23

78

T26

15

T30

63

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2506

1

T23

50

T26

10

T30

56

auto[1]

3742

1

T23

110

T26

22

T30

88

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3597

1

T23

83

T26

21

T30

80

auto[1]

2651

1

T23

77

T26

11

T30

64

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	154	1			T26	1		T30	6		T31	3
all_values[0]	auto[0]	auto[0]	auto[1]	78	1			T23	5		T30	1		T33	3
all_values[0]	auto[0]	auto[1]	auto[0]	120	1			T23	3		T30	3		T33	2
all_values[0]	auto[0]	auto[1]	auto[1]	88	1			T23	3		T26	2		T30	3
all_values[0]	auto[1]	auto[0]	auto[1]	214	1			T23	6		T26	1		T30	4
all_values[0]	auto[1]	auto[1]	auto[1]	127	1			T23	3		T30	1		T31	3
all_values[1]	auto[0]	auto[0]	auto[0]	163	1			T23	2		T26	1		T30	2
all_values[1]	auto[0]	auto[0]	auto[1]	87	1			T23	3		T26	2		T30	4
all_values[1]	auto[0]	auto[1]	auto[0]	123	1			T23	1		T30	3		T31	2
all_values[1]	auto[0]	auto[1]	auto[1]	69	1			T23	4		T30	2		T33	3
all_values[1]	auto[1]	auto[0]	auto[1]	173	1			T23	5		T30	5		T31	2
all_values[1]	auto[1]	auto[1]	auto[1]	166	1			T23	5		T26	1		T30	2
all_values[2]	auto[0]	auto[0]	auto[0]	161	1			T23	4		T26	1		T30	6
all_values[2]	auto[0]	auto[0]	auto[1]	77	1			T23	1		T30	1		T31	4
all_values[2]	auto[0]	auto[1]	auto[0]	133	1			T23	5		T30	2		T33	3
all_values[2]	auto[0]	auto[1]	auto[1]	81	1			T23	4		T26	1		T30	2
all_values[2]	auto[1]	auto[0]	auto[1]	180	1			T23	3		T26	1		T30	4
all_values[2]	auto[1]	auto[1]	auto[1]	149	1			T23	3		T26	1		T30	3
all_values[3]	auto[0]	auto[0]	auto[0]	181	1			T23	4		T30	4		T31	2
all_values[3]	auto[0]	auto[0]	auto[1]	62	1			T23	4		T26	1		T31	1
all_values[3]	auto[0]	auto[1]	auto[0]	115	1			T30	4		T31	2		T33	9
all_values[3]	auto[0]	auto[1]	auto[1]	81	1			T23	2		T26	1		T30	1
all_values[3]	auto[1]	auto[0]	auto[1]	178	1			T23	5		T26	1		T30	5
all_values[3]	auto[1]	auto[1]	auto[1]	164	1			T23	5		T26	1		T30	4
all_values[4]	auto[0]	auto[0]	auto[0]	164	1			T23	5		T26	1		T30	3
all_values[4]	auto[0]	auto[0]	auto[1]	81	1			T30	1		T31	1		T33	5
all_values[4]	auto[0]	auto[1]	auto[0]	150	1			T23	5		T26	1		T30	1
all_values[4]	auto[0]	auto[1]	auto[1]	75	1			T26	1		T30	2		T33	3
all_values[4]	auto[1]	auto[0]	auto[1]	169	1			T23	7		T26	1		T30	5
all_values[4]	auto[1]	auto[1]	auto[1]	142	1			T23	3		T30	6		T31	1
all_values[5]	auto[0]	auto[0]	auto[0]	232	1			T23	4		T26	2		T30	5
all_values[5]	auto[0]	auto[1]	auto[0]	227	1			T23	8		T26	2		T30	2
all_values[5]	auto[1]	auto[0]	auto[1]	156	1			T23	3		T30	8		T31	3
all_values[5]	auto[1]	auto[1]	auto[1]	166	1			T23	5		T30	3		T31	1
all_values[6]	auto[0]	auto[0]	auto[0]	156	1			T23	3		T30	3		T31	2
all_values[6]	auto[0]	auto[0]	auto[1]	74	1			T23	1		T26	1		T30	1
all_values[6]	auto[0]	auto[1]	auto[0]	128	1			T30	4		T31	1		T33	3
all_values[6]	auto[0]	auto[1]	auto[1]	82	1			T23	3		T26	1		T30	2
all_values[6]	auto[1]	auto[0]	auto[1]	188	1			T23	6		T26	1		T30	4
all_values[6]	auto[1]	auto[1]	auto[1]	153	1			T23	7		T26	1		T30	4
all_values[7]	auto[0]	auto[0]	auto[0]	176	1			T23	3		T30	5		T31	4
all_values[7]	auto[0]	auto[0]	auto[1]	73	1			T23	2		T30	1		T33	4
all_values[7]	auto[0]	auto[1]	auto[0]	123	1			T23	3		T26	1		T30	3
all_values[7]	auto[0]	auto[1]	auto[1]	83	1			T23	1		T26	1		T30	3
all_values[7]	auto[1]	auto[0]	auto[1]	195	1			T23	6		T26	2		T30	3
all_values[7]	auto[1]	auto[1]	auto[1]	131	1			T23	5		T30	3		T31	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal