Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2523740	1			T1	2		T2	1		T3	1
all_values[1]	2523740	1			T1	2		T2	1		T3	1
all_values[2]	2523740	1			T1	2		T2	1		T3	1
all_values[3]	2523740	1			T1	2		T2	1		T3	1
all_values[4]	2523740	1			T1	2		T2	1		T3	1
all_values[5]	2523740	1			T1	2		T2	1		T3	1
all_values[6]	2523740	1			T1	2		T2	1		T3	1
all_values[7]	2523740	1			T1	2		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19815121

1

T1

16

T2

8

T3

8

auto[1]

374799

1

T29

5789

T32

187876

T61

58

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20168357

1

T1

16

T2

8

T3

8

auto[1]

21563

1

T4

96

T16

18

T17

2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2462410	1			T1	2		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	11453	1			T4	39		T16	18		T25	171
all_values[0]	auto[1]	auto[0]	49525	1			T29	2857		T32	37564		T61	10
all_values[0]	auto[1]	auto[1]	352	1			T29	26		T32	6		T61	2
all_values[1]	auto[0]	auto[0]	2510802	1			T1	2		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	5287	1			T4	39		T25	83		T42	20
all_values[1]	auto[1]	auto[0]	7447	1			T29	1		T32	3		T61	2
all_values[1]	auto[1]	auto[1]	204	1			T29	3		T32	2		T61	4
all_values[2]	auto[0]	auto[0]	2463026	1			T1	2		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	1769	1			T4	18		T31	27		T29	15
all_values[2]	auto[1]	auto[0]	58695	1			T29	3		T32	37570		T61	3
all_values[2]	auto[1]	auto[1]	250	1			T29	1		T32	3		T61	5
all_values[3]	auto[0]	auto[0]	2494858	1			T1	2		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	221	1			T29	5		T32	8		T61	3
all_values[3]	auto[1]	auto[0]	28463	1			T29	1		T32	4		T61	6
all_values[3]	auto[1]	auto[1]	198	1			T29	3		T32	2		T61	3
all_values[4]	auto[0]	auto[0]	2464586	1			T1	2		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	246	1			T29	3		T32	3		T61	5
all_values[4]	auto[1]	auto[0]	58720	1			T32	37570		T61	1		T173	6
all_values[4]	auto[1]	auto[1]	188	1			T29	3		T32	1		T61	2
all_values[5]	auto[0]	auto[0]	2459730	1			T1	2		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	357	1			T17	2		T24	7		T27	1
all_values[5]	auto[1]	auto[0]	63452	1			T29	2		T32	37566		T61	3
all_values[5]	auto[1]	auto[1]	201	1			T29	1		T32	4		T61	3
all_values[6]	auto[0]	auto[0]	2445518	1			T1	2		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	226	1			T29	3		T32	5		T61	4
all_values[6]	auto[1]	auto[0]	77788	1			T29	2880		T32	37568		T61	4
all_values[6]	auto[1]	auto[1]	208	1			T29	2		T32	4		T61	3
all_values[7]	auto[0]	auto[0]	2494442	1			T1	2		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	190	1			T29	3		T32	6		T61	4
all_values[7]	auto[1]	auto[0]	28895	1			T29	1		T32	6		T61	3
all_values[7]	auto[1]	auto[1]	213	1			T29	5		T32	3		T61	4