Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	28477	1			T2	2		T3	6		T4	105
auto[SpiFlashAddrCfg]	6427	1			T1	4		T2	2		T3	8
auto[SpiFlashAddr3b]	7517	1			T3	4		T4	33		T5	4
auto[SpiFlashAddr4b]	6348	1			T1	2		T2	2		T3	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28082

1

T1

6

T3

20

T4

125

auto[1]

20687

1

T2

6

T4

65

T16

18

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26055

1

T1

2

T2

2

T3

12

auto[1]

22714

1

T1

4

T2

4

T3

8

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	32508	1			T2	2		T3	8		T4	127
values[1]	920	1			T1	1		T2	2		T4	2
values[2]	1209	1			T4	8		T9	6		T16	2
values[3]	1163	1			T1	1		T4	1		T5	4
values[4]	1223	1			T4	4		T5	6		T16	1
values[5]	1160	1			T1	2		T4	3		T16	1
values[6]	1229	1			T3	2		T4	2		T16	4
values[7]	1198	1			T2	2		T3	2		T4	3
values[8]	8159	1			T1	2		T3	8		T4	40

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23265

1

T2

6

T3

20

T5

22

auto[1]

25504

1

T1

6

T4

190

T39

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

46951

1

T1

6

T2

6

T3

20

write

1818

1

T4

15

T16

4

T21

7

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

16242

1

T1

3

T3

8

T4

57

valids[0x1]

32527

1

T1

3

T2

6

T3

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1345	1			T4	4		T16	1		T37	2
internal_process_ops[0x5a]	1346	1			T4	5		T5	4		T16	1
internal_process_ops[0x05]	16884	1			T4	72		T9	4		T16	7
internal_process_ops[0x35]	1296	1			T3	2		T4	1		T36	4
internal_process_ops[0x15]	1322	1			T3	2		T4	5		T16	4
internal_process_ops[0x03]	849	1			T1	2		T4	3		T16	2
internal_process_ops[0x0b]	878	1			T1	1		T16	2		T18	2
internal_process_ops[0x3b]	897	1			T4	1		T9	6		T16	1
internal_process_ops[0x6b]	875	1			T1	2		T4	3		T5	4
internal_process_ops[0xbb]	883	1			T4	3		T36	4		T18	2
internal_process_ops[0xeb]	836	1			T1	1		T4	1		T16	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47886

1

T1

6

T2

6

T3

20

auto[1]

883

1

T4

13

T16

4

T21

3

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47047

1

T1

6

T2

6

T3

20

auto[1]

1722

1

T4

5

T16

2

T21

6

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

7773

1

T3

6

T5

8

T9

4

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

4580

1

T2

2

T16

10

T18

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1767

1

T3

8

T5

10

T16

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1449

1

T2

2

T16

2

T18

9

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2068

1

T3

4

T5

4

T16

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1668

1

T16

2

T18

5

T21

9

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1769

1

T3

2

T9

6

T16

3

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1423

1

T2

2

T16

1

T18

5

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

57

1

T21

1

T174

1

T175

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

44

1

T16

1

T21

1

T26

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

46

1

T21

1

T30

2

T35

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

42

1

T29

2

T30

2

T176

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

50

1

T31

1

T29

2

T30

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

49

1

T26

1

T31

2

T29

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

41

1

T31

2

T32

1

T30

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

51

1

T176

2

T155

1

T177

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

69

1

T29

1

T30

2

T178

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

31

1

T31

1

T29

2

T35

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

48

1

T26

2

T31

1

T29

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

38

1

T33

2

T34

2

T30

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

53

1

T179

2

T176

1

T180

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

34

1

T21

2

T30

1

T176

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

38

1

T21

2

T31

1

T29

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

77

1

T16

3

T26

2

T31

3

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9223

1

T4

82

T25

91

T42

47

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6441

1

T4

21

T25

76

T42

8

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1501

1

T1

4

T4

14

T39

1

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1269

1

T4

5

T25

11

T42

11

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1627

1

T4

14

T25

34

T42

8

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1708

1

T4

17

T25

23

T42

18

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1387

1

T1

2

T4

10

T25

30

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1298

1

T4

12

T25

22

T42

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

76

1

T29

4

T89

2

T178

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

75

1

T4

2

T29

4

T57

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

61

1

T57

2

T89

3

T139

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

59

1

T29

1

T89

1

T178

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

64

1

T25

2

T57

1

T178

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

68

1

T25

2

T29

2

T139

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

74

1

T42

1

T29

2

T57

6

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

44

1

T4

5

T82

1

T181

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

72

1

T25

1

T29

1

T57

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

78

1

T4

1

T29

4

T57

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

66

1

T25

1

T57

2

T89

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

44

1

T4

1

T25

3

T42

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

62

1

T25

1

T89

1

T178

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

85

1

T4

2

T25

1

T29

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

58

1

T4

2

T29

1

T139

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

64

1

T4

2

T29

2

T57

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3160	1			T15	10		T16	9		T28	10
auto[0]	values[0]	valids[0x1]	11381	1			T2	2		T3	8		T5	2
auto[0]	values[1]	valids[0x1]	404	1			T2	2		T18	5		T21	7
auto[0]	values[2]	valids[0x0]	423	1			T9	6		T36	2		T21	5
auto[0]	values[2]	valids[0x1]	255	1			T16	2		T26	3		T31	1
auto[0]	values[3]	valids[0x0]	411	1			T5	4		T18	3		T21	1
auto[0]	values[3]	valids[0x1]	218	1			T21	2		T137	4		T29	2
auto[0]	values[4]	valids[0x0]	413	1			T5	4		T16	1		T36	4
auto[0]	values[4]	valids[0x1]	269	1			T5	2		T18	4		T21	1
auto[0]	values[5]	valids[0x0]	437	1			T16	1		T18	5		T26	2
auto[0]	values[5]	valids[0x1]	226	1			T81	2		T26	5		T137	4
auto[0]	values[6]	valids[0x0]	432	1			T16	1		T18	4		T21	3
auto[0]	values[6]	valids[0x1]	237	1			T3	2		T16	3		T21	1
auto[0]	values[7]	valids[0x0]	396	1			T21	2		T26	1		T182	2
auto[0]	values[7]	valids[0x1]	245	1			T2	2		T3	2		T5	6
auto[0]	values[8]	valids[0x0]	2862	1			T3	8		T16	5		T18	6
auto[0]	values[8]	valids[0x1]	1496	1			T5	4		T16	3		T18	7
auto[1]	values[0]	valids[0x0]	3687	1			T4	24		T25	54		T42	24
auto[1]	values[0]	valids[0x1]	14280	1			T4	103		T25	143		T42	46
auto[1]	values[1]	valids[0x1]	516	1			T1	1		T4	2		T25	5
auto[1]	values[2]	valids[0x0]	320	1			T4	1		T25	2		T42	1
auto[1]	values[2]	valids[0x1]	211	1			T4	7		T25	6		T29	3
auto[1]	values[3]	valids[0x0]	327	1			T1	1		T4	1		T25	3
auto[1]	values[3]	valids[0x1]	207	1			T25	1		T42	1		T29	2
auto[1]	values[4]	valids[0x0]	336	1			T4	4		T25	10		T42	2
auto[1]	values[4]	valids[0x1]	205	1			T42	1		T29	2		T57	2
auto[1]	values[5]	valids[0x0]	287	1			T25	5		T42	5		T29	7
auto[1]	values[5]	valids[0x1]	210	1			T1	2		T4	3		T25	7
auto[1]	values[6]	valids[0x0]	327	1			T4	1		T39	1		T25	6
auto[1]	values[6]	valids[0x1]	233	1			T4	1		T25	4		T29	8
auto[1]	values[7]	valids[0x0]	330	1			T4	2		T25	5		T42	7
auto[1]	values[7]	valids[0x1]	227	1			T4	1		T25	3		T29	2
auto[1]	values[8]	valids[0x0]	2094	1			T1	2		T4	24		T25	29
auto[1]	values[8]	valids[0x1]	1707	1			T4	16		T25	36		T42	13