Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2985567

1

T1

925

T2

1

T3

1

auto[1]

15530

1

T4

70

T16

6

T21

61

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

968100

1

T1

925

T2

1

T3

1

auto[1]

2032997

1

T4

4570

T16

6632

T37

8684

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	601531	1			T1	23		T2	1		T3	1
auto[524288:1048575]	313664	1			T1	106		T4	30		T15	678
auto[1048576:1572863]	316808	1			T1	118		T9	50		T16	2933
auto[1572864:2097151]	326922	1			T4	1		T15	610		T16	1
auto[2097152:2621439]	405816	1			T1	678		T4	33		T9	54
auto[2621440:3145727]	362790	1			T9	52		T28	1		T37	5306
auto[3145728:3670015]	376351	1			T4	3251		T9	83		T15	340
auto[3670016:4194303]	297215	1			T9	26		T16	3188		T37	1063

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2053163

1

T1

11

T2

1

T3

1

auto[1]

947934

1

T1

914

T4

2

T9

302

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2627862

1

T1

925

T2

1

T3

1

auto[1]

373235

1

T4

1275

T15

1509

T28

450

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	239224	1			T1	23		T2	1		T3	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	311607	1			T4	11		T16	256		T37	1749
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	76856	1			T1	106		T4	6		T15	4
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	192078	1			T4	1		T16	257		T38	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	95679	1			T1	118		T9	50		T16	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	173068	1			T16	2928		T21	133		T25	515
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	107986	1			T4	1		T15	610		T16	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	192495	1			T37	1527		T38	49		T25	1677
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	124001	1			T1	678		T4	3		T9	54
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	229849	1			T4	5		T38	2		T21	2737
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	105895	1			T9	52		T37	959		T18	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	197740	1			T37	4347		T21	1422		T25	2961
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	120757	1			T9	83		T15	74		T37	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	201887	1			T4	3251		T18	1		T38	513
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	84809	1			T9	26		T16	1		T37	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	161838	1			T16	3187		T37	1061		T21	8
auto[0]	auto[1]	auto[0:524287]	auto[0]	1938	1			T4	3		T15	291		T28	92
auto[0]	auto[1]	auto[0:524287]	auto[1]	46315	1			T4	1236		T25	451		T31	263
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	945	1			T4	5		T15	674		T28	71
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	41334	1			T4	1		T31	1708		T29	256
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1620	1			T28	68		T31	3		T29	9
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	44636	1			T31	640		T29	1174		T89	4
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1674	1			T28	213		T21	5		T29	8
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	23385	1			T21	521		T29	259		T82	128
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1854	1			T4	1		T15	278		T18	5
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	48448	1			T18	2879		T21	512		T29	1769
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	244	1			T28	1		T31	1		T29	6
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	56480	1			T29	525		T32	768		T89	769
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	2017	1			T15	266		T28	5		T25	4
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	49794	1			T25	257		T26	512		T31	5
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	877	1			T21	9		T25	5		T32	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	48237	1			T21	257		T25	1837		T29	84
auto[1]	auto[0]	auto[0:524287]	auto[0]	224	1			T4	2		T25	2		T31	3
auto[1]	auto[0]	auto[0:524287]	auto[1]	1779	1			T4	15		T25	3		T31	9
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	204	1			T16	1		T25	1		T26	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1747	1			T16	2		T25	1		T26	18
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	163	1			T16	1		T25	2		T26	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1146	1			T16	2		T25	2		T26	40
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	153	1			T25	1		T42	1		T29	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1008	1			T25	1		T42	2		T29	5
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	141	1			T4	1		T25	1		T26	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1141	1			T4	23		T25	1		T26	11
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	185	1			T21	1		T25	1		T31	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1591	1			T21	7		T25	1		T29	33
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	168	1			T21	1		T25	3		T26	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1166	1			T21	17		T25	20		T26	5
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	162	1			T21	2		T25	1		T29	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1115	1			T21	13		T25	6		T29	5
auto[1]	auto[1]	auto[0:524287]	auto[0]	56	1			T4	1		T25	1		T31	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	388	1			T4	11		T25	2		T31	4
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	38	1			T4	1		T44	1		T176	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	462	1			T4	16		T44	40		T176	9
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	41	1			T294	1		T155	2		T181	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	455	1			T155	1		T181	18		T177	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	26	1			T21	1		T29	3		T298	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	195	1			T29	33		T298	3		T320	4
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	38	1			T29	2		T57	1		T178	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	344	1			T29	18		T178	1		T294	4
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	54	1			T29	3		T89	1		T174	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	601	1			T29	90		T89	4		T174	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	44	1			T25	1		T139	1		T82	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	518	1			T25	7		T139	2		T82	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	27	1			T21	1		T25	1		T89	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	150	1			T21	18		T89	6		T82	27

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1677150	1			T1	11		T2	1		T3	1
auto[0]	auto[0]	auto[1]	938619	1			T1	914		T4	1		T9	302
auto[0]	auto[1]	auto[0]	360814	1			T4	1245		T15	21		T28	83
auto[0]	auto[1]	auto[1]	8984	1			T4	1		T15	1488		T28	367
auto[1]	auto[0]	auto[0]	11829	1			T4	41		T16	6		T21	38
auto[1]	auto[0]	auto[1]	264	1			T21	3		T25	1		T26	1
auto[1]	auto[1]	auto[0]	3370	1			T4	29		T21	19		T25	10
auto[1]	auto[1]	auto[1]	67	1			T21	1		T25	2		T29	1