Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13764

1

T3

20

T5

22

T9

10

auto[1]

9501

1

T2

6

T16

18

T18

21

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2544	1			T36	10		T21	28		T26	83
values[1]	3040	1			T21	20		T31	21		T29	157
values[2]	3219	1			T2	6		T5	22		T16	46
values[3]	2758	1			T9	10		T37	10		T18	20
values[4]	2990	1			T18	20		T136	2		T137	20
values[5]	3002	1			T3	20		T15	10		T28	10
values[6]	2760	1			T21	40		T31	22		T29	43
values[7]	2952	1			T21	53		T26	56		T31	60

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2806	1			T28	10		T18	40		T26	63
values[1]	2505	1			T37	10		T21	20		T31	22
values[2]	2992	1			T41	10		T81	4		T21	48
values[3]	2878	1			T18	20		T183	12		T31	40
values[4]	3416	1			T2	6		T5	22		T9	10
values[5]	2650	1			T16	26		T135	6		T99	4
values[6]	3165	1			T15	10		T36	10		T21	73
values[7]	2853	1			T3	20		T38	6		T26	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	180	1			T26	57		T31	10		T186	6
auto[0]	values[0]	values[1]	251	1			T29	12		T30	33		T155	11
auto[0]	values[0]	values[2]	107	1			T21	23		T30	2		T322	4
auto[0]	values[0]	values[3]	205	1			T222	11		T323	8		T246	13
auto[0]	values[0]	values[4]	152	1			T177	11		T220	14		T191	13
auto[0]	values[0]	values[5]	232	1			T135	6		T32	10		T30	42
auto[0]	values[0]	values[6]	154	1			T36	10		T180	11		T200	18
auto[0]	values[0]	values[7]	186	1			T26	10		T31	12		T71	10
auto[0]	values[1]	values[0]	181	1			T196	9		T324	4		T318	4
auto[0]	values[1]	values[1]	160	1			T21	16		T202	2		T234	12
auto[0]	values[1]	values[2]	346	1			T31	10		T155	10		T198	34
auto[0]	values[1]	values[3]	229	1			T35	30		T221	2		T325	6
auto[0]	values[1]	values[4]	269	1			T32	13		T164	4		T176	9
auto[0]	values[1]	values[5]	139	1			T29	12		T179	36		T326	6
auto[0]	values[1]	values[6]	267	1			T29	104		T155	19		T222	12
auto[0]	values[1]	values[7]	198	1			T29	17		T30	9		T190	12
auto[0]	values[2]	values[0]	146	1			T172	12		T205	12		T327	2
auto[0]	values[2]	values[1]	218	1			T29	7		T328	2		T329	2
auto[0]	values[2]	values[2]	162	1			T98	6		T204	16		T197	8
auto[0]	values[2]	values[3]	372	1			T29	13		T30	37		T195	7
auto[0]	values[2]	values[4]	422	1			T5	22		T16	10		T330	2
auto[0]	values[2]	values[5]	257	1			T16	18		T239	16		T155	23
auto[0]	values[2]	values[6]	152	1			T21	16		T174	11		T205	14
auto[0]	values[2]	values[7]	208	1			T35	10		T174	15		T180	10
auto[0]	values[3]	values[0]	320	1			T18	10		T35	6		T74	2
auto[0]	values[3]	values[1]	172	1			T37	10		T316	6		T175	12
auto[0]	values[3]	values[2]	188	1			T81	4		T21	11		T54	6
auto[0]	values[3]	values[3]	286	1			T29	12		T187	22		T191	13
auto[0]	values[3]	values[4]	232	1			T9	10		T32	10		T222	12
auto[0]	values[3]	values[5]	149	1			T178	13		T72	18		T297	6
auto[0]	values[3]	values[6]	247	1			T176	14		T222	15		T226	10
auto[0]	values[3]	values[7]	129	1			T195	6		T331	8		T332	8
auto[0]	values[4]	values[0]	180	1			T31	15		T30	12		T333	29
auto[0]	values[4]	values[1]	182	1			T225	2		T35	15		T168	8
auto[0]	values[4]	values[2]	176	1			T210	2		T30	14		T180	8
auto[0]	values[4]	values[3]	133	1			T18	14		T183	12		T176	11
auto[0]	values[4]	values[4]	445	1			T30	12		T176	85		T180	17
auto[0]	values[4]	values[5]	205	1			T213	14		T35	13		T167	4
auto[0]	values[4]	values[6]	209	1			T334	14		T198	13		T252	11
auto[0]	values[4]	values[7]	265	1			T212	12		T32	22		T30	10
auto[0]	values[5]	values[0]	363	1			T28	10		T18	15		T138	12
auto[0]	values[5]	values[1]	207	1			T29	20		T233	24		T232	4
auto[0]	values[5]	values[2]	284	1			T205	10		T211	10		T231	11
auto[0]	values[5]	values[3]	191	1			T31	12		T30	10		T178	7
auto[0]	values[5]	values[4]	120	1			T35	10		T155	10		T229	4
auto[0]	values[5]	values[5]	127	1			T214	4		T45	9		T185	9
auto[0]	values[5]	values[6]	194	1			T15	10		T29	9		T306	45
auto[0]	values[5]	values[7]	261	1			T3	20		T38	6		T31	7
auto[0]	values[6]	values[0]	193	1			T178	15		T155	18		T175	14
auto[0]	values[6]	values[1]	160	1			T31	14		T176	13		T180	16
auto[0]	values[6]	values[2]	115	1			T169	14		T195	10		T264	15
auto[0]	values[6]	values[3]	224	1			T29	31		T30	13		T35	8
auto[0]	values[6]	values[4]	252	1			T21	31		T35	14		T335	8
auto[0]	values[6]	values[5]	343	1			T32	12		T205	31		T177	33
auto[0]	values[6]	values[6]	297	1			T205	13		T222	7		T195	16
auto[0]	values[6]	values[7]	105	1			T336	6		T195	15		T337	4
auto[0]	values[7]	values[0]	192	1			T31	13		T219	16		T203	4
auto[0]	values[7]	values[1]	158	1			T177	15		T191	10		T317	72
auto[0]	values[7]	values[2]	198	1			T31	16		T155	14		T75	4
auto[0]	values[7]	values[3]	124	1			T31	6		T29	7		T238	12
auto[0]	values[7]	values[4]	165	1			T26	6		T155	11		T205	23
auto[0]	values[7]	values[5]	151	1			T99	4		T177	11		T246	6
auto[0]	values[7]	values[6]	424	1			T21	14		T30	6		T176	82
auto[0]	values[7]	values[7]	205	1			T29	11		T169	16		T205	23
auto[1]	values[0]	values[0]	125	1			T26	6		T31	10		T33	8
auto[1]	values[0]	values[1]	212	1			T29	8		T30	7		T155	9
auto[1]	values[0]	values[2]	51	1			T21	5		T30	18		T226	9
auto[1]	values[0]	values[3]	50	1			T222	9		T246	7		T277	7
auto[1]	values[0]	values[4]	127	1			T224	14		T177	10		T220	10
auto[1]	values[0]	values[5]	195	1			T32	10		T30	6		T222	7
auto[1]	values[0]	values[6]	83	1			T180	9		T195	8		T199	8
auto[1]	values[0]	values[7]	234	1			T26	10		T31	25		T207	9
auto[1]	values[1]	values[0]	96	1			T196	11		T208	8		T246	39
auto[1]	values[1]	values[1]	117	1			T21	4		T176	43		T338	2
auto[1]	values[1]	values[2]	176	1			T31	11		T155	10		T198	5
auto[1]	values[1]	values[3]	186	1			T35	13		T191	8		T264	10
auto[1]	values[1]	values[4]	207	1			T32	7		T176	82		T155	9
auto[1]	values[1]	values[5]	98	1			T29	8		T179	4		T198	11
auto[1]	values[1]	values[6]	205	1			T29	9		T155	10		T251	16
auto[1]	values[1]	values[7]	166	1			T29	7		T30	24		T169	9
auto[1]	values[2]	values[0]	88	1			T205	8		T191	5		T231	21
auto[1]	values[2]	values[1]	185	1			T29	27		T177	11		T198	12
auto[1]	values[2]	values[2]	86	1			T41	10		T35	7		T199	6
auto[1]	values[2]	values[3]	134	1			T29	7		T30	40		T195	13
auto[1]	values[2]	values[4]	353	1			T2	6		T16	10		T196	9
auto[1]	values[2]	values[5]	148	1			T16	8		T194	20		T155	9
auto[1]	values[2]	values[6]	191	1			T21	4		T174	18		T205	8
auto[1]	values[2]	values[7]	97	1			T35	11		T174	5		T180	12
auto[1]	values[3]	values[0]	190	1			T18	10		T35	14		T191	11
auto[1]	values[3]	values[1]	41	1			T175	9		T205	7		T272	4
auto[1]	values[3]	values[2]	114	1			T21	9		T199	10		T208	22
auto[1]	values[3]	values[3]	187	1			T29	8		T191	18		T159	11
auto[1]	values[3]	values[4]	145	1			T32	11		T222	9		T264	10
auto[1]	values[3]	values[5]	119	1			T178	11		T259	21		T254	21
auto[1]	values[3]	values[6]	132	1			T176	9		T222	11		T226	11
auto[1]	values[3]	values[7]	107	1			T195	23		T332	12		T243	10
auto[1]	values[4]	values[0]	159	1			T137	20		T31	11		T30	21
auto[1]	values[4]	values[1]	117	1			T35	5		T176	17		T218	12
auto[1]	values[4]	values[2]	250	1			T30	12		T180	12		T196	9
auto[1]	values[4]	values[3]	121	1			T18	6		T176	9		T180	3
auto[1]	values[4]	values[4]	143	1			T30	8		T176	8		T180	10
auto[1]	values[4]	values[5]	71	1			T35	7		T176	10		T195	9
auto[1]	values[4]	values[6]	153	1			T182	6		T198	7		T252	9
auto[1]	values[4]	values[7]	181	1			T136	2		T32	19		T30	10
auto[1]	values[5]	values[0]	140	1			T18	5		T34	4		T169	15
auto[1]	values[5]	values[1]	149	1			T29	7		T155	9		T208	18
auto[1]	values[5]	values[2]	263	1			T205	10		T211	15		T231	9
auto[1]	values[5]	values[3]	195	1			T31	8		T30	16		T178	13
auto[1]	values[5]	values[4]	131	1			T193	16		T35	11		T155	10
auto[1]	values[5]	values[5]	93	1			T45	11		T185	11		T269	9
auto[1]	values[5]	values[6]	70	1			T29	12		T177	4		T310	9
auto[1]	values[5]	values[7]	214	1			T31	13		T35	15		T155	15
auto[1]	values[6]	values[0]	140	1			T178	5		T155	6		T175	7
auto[1]	values[6]	values[1]	112	1			T31	8		T176	7		T180	4
auto[1]	values[6]	values[2]	201	1			T169	43		T195	39		T264	6
auto[1]	values[6]	values[3]	102	1			T29	12		T30	7		T35	14
auto[1]	values[6]	values[4]	83	1			T21	9		T35	7		T339	10
auto[1]	values[6]	values[5]	171	1			T32	8		T205	9		T177	6
auto[1]	values[6]	values[6]	176	1			T205	7		T222	14		T195	12
auto[1]	values[6]	values[7]	86	1			T195	20		T340	20		T254	7
auto[1]	values[7]	values[0]	113	1			T31	7		T192	18		T159	6
auto[1]	values[7]	values[1]	64	1			T177	5		T191	10		T184	9
auto[1]	values[7]	values[2]	275	1			T31	4		T155	6		T272	10
auto[1]	values[7]	values[3]	139	1			T31	14		T29	15		T35	11
auto[1]	values[7]	values[4]	170	1			T26	50		T155	14		T205	21
auto[1]	values[7]	values[5]	152	1			T177	9		T246	46		T259	16
auto[1]	values[7]	values[6]	211	1			T21	39		T30	14		T176	13
auto[1]	values[7]	values[7]	211	1			T29	9		T169	4		T205	79