Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	297	1			T21	4		T26	2		T183	4
auto[ReadAddrCrossIntoMailbox]	241	1			T16	1		T21	4		T26	1
auto[ReadAddrCrossOutOfMailbox]	236	1			T16	1		T18	2		T21	7
auto[ReadAddrCrossAllMailbox]	169	1			T18	1		T21	2		T183	4
auto[ReadAddrOutsideMailbox]	2862	1			T5	4		T9	6		T16	6

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1909

1

T5

2

T9

3

T16

3

auto[1]

1896

1

T5

2

T9

3

T16

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	584	1			T16	2		T18	1		T81	2
read_ops[0x0b]	643	1			T16	2		T18	2		T21	5
read_ops[0x3b]	697	1			T9	6		T16	1		T18	1
read_ops[0x6b]	636	1			T5	4		T16	2		T18	1
read_ops[0xbb]	643	1			T36	4		T18	2		T38	2
read_ops[0xeb]	602	1			T16	1		T18	1		T21	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	22	1			T183	1		T31	1		T176	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	23	1			T183	1		T174	1		T175	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T16	1		T21	1		T30	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	15	1			T30	1		T305	1		T222	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	11	1			T176	1		T155	1		T222	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	15	1			T29	1		T205	2		T341	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T18	1		T21	2		T183	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T183	1		T30	1		T205	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	227	1			T81	1		T26	2		T135	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	220	1			T16	1		T81	1		T21	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T21	1		T234	1		T221	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T31	1		T29	1		T30	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	12	1			T175	1		T342	1		T222	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T21	1		T29	1		T180	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T175	1		T205	1		T343	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T18	1		T21	1		T31	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	9	1			T32	1		T196	1		T159	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T29	2		T179	1		T155	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	252	1			T21	2		T26	2		T138	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	226	1			T16	2		T18	1		T138	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	21	1			T26	1		T183	1		T210	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T183	1		T210	1		T179	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T21	1		T30	2		T35	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T21	1		T31	1		T169	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T21	2		T30	1		T201	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T21	1		T31	2		T29	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T31	2		T177	1		T222	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	11	1			T32	1		T246	1		T344	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	279	1			T9	3		T21	3		T31	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	245	1			T9	3		T16	1		T18	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	21	1			T21	2		T232	1		T345	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	20	1			T232	1		T155	1		T205	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	11	1			T26	1		T30	1		T176	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	16	1			T29	1		T30	1		T180	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T16	1		T21	1		T178	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	16	1			T30	2		T345	1		T222	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	9	1			T30	1		T201	1		T260	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T201	1		T333	1		T199	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	251	1			T5	2		T16	1		T18	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	256	1			T5	2		T21	2		T31	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T26	1		T30	1		T35	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	22	1			T21	1		T30	1		T175	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T183	1		T179	1		T180	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T183	1		T29	2		T155	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	17	1			T179	1		T178	1		T186	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T18	1		T21	1		T186	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T183	1		T35	2		T186	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T183	1		T29	1		T30	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	231	1			T36	2		T38	1		T81	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	244	1			T36	2		T18	1		T38	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	21	1			T234	1		T155	1		T72	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T30	2		T234	1		T72	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T32	1		T179	1		T30	3
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T31	1		T174	1		T195	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T21	1		T183	1		T35	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T183	1		T31	3		T30	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T29	1		T171	1		T176	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T171	1		T195	1		T246	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	235	1			T18	1		T21	1		T31	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	196	1			T16	1		T26	2		T31	1