Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2523740	1			T1	2		T2	1		T3	1
all_pins[1]	2523740	1			T1	2		T2	1		T3	1
all_pins[2]	2523740	1			T1	2		T2	1		T3	1
all_pins[3]	2523740	1			T1	2		T2	1		T3	1
all_pins[4]	2523740	1			T1	2		T2	1		T3	1
all_pins[5]	2523740	1			T1	2		T2	1		T3	1
all_pins[6]	2523740	1			T1	2		T2	1		T3	1
all_pins[7]	2523740	1			T1	2		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20111456	1			T1	16		T2	8		T3	8
values[0x1]	78464	1			T29	2917		T32	36185		T61	26
transitions[0x0=>0x1]	77215	1			T29	2915		T32	35746		T61	21
transitions[0x1=>0x0]	77230	1			T29	2915		T32	35746		T61	21

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2523382	1			T1	2		T2	1		T3	1
all_pins[0]	values[0x1]	358	1			T29	28		T32	8		T61	2
all_pins[0]	transitions[0x0=>0x1]	314	1			T29	28		T32	7		T61	2
all_pins[0]	transitions[0x1=>0x0]	163	1			T29	3		T32	1		T61	4
all_pins[1]	values[0x0]	2523533	1			T1	2		T2	1		T3	1
all_pins[1]	values[0x1]	207	1			T29	3		T32	2		T61	4
all_pins[1]	transitions[0x0=>0x1]	163	1			T29	3		T32	2		T61	1
all_pins[1]	transitions[0x1=>0x0]	208	1			T29	1		T32	4		T61	2
all_pins[2]	values[0x0]	2523488	1			T1	2		T2	1		T3	1
all_pins[2]	values[0x1]	252	1			T29	1		T32	4		T61	5
all_pins[2]	transitions[0x0=>0x1]	209	1			T29	1		T32	3		T61	5
all_pins[2]	transitions[0x1=>0x0]	155	1			T29	3		T32	1		T61	3
all_pins[3]	values[0x0]	2523542	1			T1	2		T2	1		T3	1
all_pins[3]	values[0x1]	198	1			T29	3		T32	2		T61	3
all_pins[3]	transitions[0x0=>0x1]	150	1			T29	3		T32	2		T61	3
all_pins[3]	transitions[0x1=>0x0]	140	1			T29	3		T32	1		T61	2
all_pins[4]	values[0x0]	2523552	1			T1	2		T2	1		T3	1
all_pins[4]	values[0x1]	188	1			T29	3		T32	1		T61	2
all_pins[4]	transitions[0x0=>0x1]	140	1			T29	3		T32	1		T61	1
all_pins[4]	transitions[0x1=>0x0]	1202	1			T29	1		T32	447		T61	2
all_pins[5]	values[0x0]	2522490	1			T1	2		T2	1		T3	1
all_pins[5]	values[0x1]	1250	1			T29	1		T32	447		T61	3
all_pins[5]	transitions[0x0=>0x1]	347	1			T29	1		T32	11		T61	2
all_pins[5]	transitions[0x1=>0x0]	74895	1			T29	2873		T32	35282		T61	2
all_pins[6]	values[0x0]	2447942	1			T1	2		T2	1		T3	1
all_pins[6]	values[0x1]	75798	1			T29	2873		T32	35718		T61	3
all_pins[6]	transitions[0x0=>0x1]	75746	1			T29	2872		T32	35718		T61	3
all_pins[6]	transitions[0x1=>0x0]	161	1			T29	4		T32	3		T61	4
all_pins[7]	values[0x0]	2523527	1			T1	2		T2	1		T3	1
all_pins[7]	values[0x1]	213	1			T29	5		T32	3		T61	4
all_pins[7]	transitions[0x0=>0x1]	146	1			T29	4		T32	2		T61	4
all_pins[7]	transitions[0x1=>0x0]	306	1			T29	27		T32	7		T61	2