Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.63	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	2	126	98.44

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	2	126	98.44	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3274	1			T37	10		T21	40		T99	4
values[1]	2914	1			T28	10		T26	20		T138	12
values[2]	3246	1			T9	10		T36	10		T18	20
values[3]	2905	1			T21	53		T183	12		T31	20
values[4]	2673	1			T15	10		T21	40		T26	63
values[5]	2456	1			T2	6		T3	20		T5	22
values[6]	3222	1			T16	46		T38	6		T81	4
values[7]	2575	1			T18	20		T21	20		T98	6

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2935	1			T3	20		T26	63		T136	2
values[1]	2558	1			T18	20		T21	28		T182	6
values[2]	2976	1			T9	10		T28	10		T21	73
values[3]	3133	1			T16	20		T36	10		T21	20
values[4]	2920	1			T18	40		T26	56		T138	12
values[5]	2890	1			T15	10		T37	10		T38	6
values[6]	2983	1			T2	6		T16	26		T81	4
values[7]	2870	1			T5	22		T31	46		T29	191

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22899

1

T2

6

T3

20

T5

22

auto[1]

366

1

T16

4

T21

3

T26

4

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	2	126	98.44	2

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[5]]	[values[4]]	0	1	1
[auto[1]]	[values[5]]	[values[6]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	461	1			T29	20		T30	25		T35	20
auto[0]	values[0]	values[1]	261	1			T99	4		T155	20		T77	20
auto[0]	values[0]	values[2]	469	1			T169	57		T184	19		T185	33
auto[0]	values[0]	values[3]	360	1			T34	2		T30	20		T186	6
auto[0]	values[0]	values[4]	303	1			T187	22		T188	8		T189	10
auto[0]	values[0]	values[5]	417	1			T37	10		T21	40		T176	20
auto[0]	values[0]	values[6]	513	1			T32	20		T30	39		T176	17
auto[0]	values[0]	values[7]	438	1			T29	110		T30	33		T164	4
auto[0]	values[1]	values[0]	313	1			T190	12		T45	20		T191	49
auto[0]	values[1]	values[1]	275	1			T31	33		T180	20		T192	12
auto[0]	values[1]	values[2]	293	1			T28	10		T30	35		T177	29
auto[0]	values[1]	values[3]	275	1			T26	19		T29	20		T193	16
auto[0]	values[1]	values[4]	313	1			T138	12		T31	19		T32	20
auto[0]	values[1]	values[5]	448	1			T32	20		T35	41		T194	20
auto[0]	values[1]	values[6]	488	1			T30	61		T169	20		T176	19
auto[0]	values[1]	values[7]	446	1			T31	42		T30	20		T176	26
auto[0]	values[2]	values[0]	477	1			T155	23		T195	20		T196	65
auto[0]	values[2]	values[1]	290	1			T197	8		T198	39		T199	20
auto[0]	values[2]	values[2]	372	1			T9	10		T31	20		T180	20
auto[0]	values[2]	values[3]	314	1			T36	10		T175	20		T177	20
auto[0]	values[2]	values[4]	585	1			T18	20		T26	54		T176	68
auto[0]	values[2]	values[5]	412	1			T29	27		T178	23		T200	18
auto[0]	values[2]	values[6]	404	1			T201	12		T202	2		T203	4
auto[0]	values[2]	values[7]	343	1			T29	20		T30	20		T35	20
auto[0]	values[3]	values[0]	187	1			T204	16		T176	20		T205	19
auto[0]	values[3]	values[1]	245	1			T35	25		T205	44		T206	4
auto[0]	values[3]	values[2]	366	1			T21	51		T31	20		T29	20
auto[0]	values[3]	values[3]	662	1			T29	23		T74	2		T177	18
auto[0]	values[3]	values[4]	426	1			T172	12		T207	20		T208	25
auto[0]	values[3]	values[5]	394	1			T183	12		T32	41		T205	20
auto[0]	values[3]	values[6]	319	1			T168	8		T155	20		T209	4
auto[0]	values[3]	values[7]	269	1			T210	2		T35	19		T211	24
auto[0]	values[4]	values[0]	416	1			T26	62		T136	2		T32	20
auto[0]	values[4]	values[1]	338	1			T174	20		T167	4		T180	20
auto[0]	values[4]	values[2]	307	1			T21	19		T212	12		T90	20
auto[0]	values[4]	values[3]	298	1			T21	20		T213	14		T171	10
auto[0]	values[4]	values[4]	216	1			T214	4		T215	20		T216	32
auto[0]	values[4]	values[5]	292	1			T15	10		T217	8		T176	23
auto[0]	values[4]	values[6]	556	1			T176	90		T72	18		T218	12
auto[0]	values[4]	values[7]	206	1			T219	16		T220	20		T195	27
auto[0]	values[5]	values[0]	385	1			T3	20		T30	31		T35	21
auto[0]	values[5]	values[1]	269	1			T18	20		T221	2		T205	20
auto[0]	values[5]	values[2]	348	1			T222	23		T195	49		T223	18
auto[0]	values[5]	values[3]	290	1			T35	18		T176	89		T224	14
auto[0]	values[5]	values[4]	320	1			T225	2		T205	20		T226	54
auto[0]	values[5]	values[5]	333	1			T41	10		T155	29		T222	26
auto[0]	values[5]	values[6]	95	1			T2	6		T205	20		T227	4
auto[0]	values[5]	values[7]	379	1			T5	22		T169	70		T228	4
auto[0]	values[6]	values[0]	340	1			T229	4		T230	4		T231	26
auto[0]	values[6]	values[1]	555	1			T21	28		T31	20		T33	6
auto[0]	values[6]	values[2]	348	1			T135	6		T31	22		T29	19
auto[0]	values[6]	values[3]	572	1			T16	19		T137	20		T178	20
auto[0]	values[6]	values[4]	387	1			T178	20		T232	4		T35	21
auto[0]	values[6]	values[5]	281	1			T38	6		T233	24		T198	20
auto[0]	values[6]	values[6]	285	1			T16	23		T81	4		T29	17
auto[0]	values[6]	values[7]	411	1			T29	24		T30	26		T234	12
auto[0]	values[7]	values[0]	316	1			T29	42		T35	20		T54	6
auto[0]	values[7]	values[1]	274	1			T182	6		T235	31		T176	48
auto[0]	values[7]	values[2]	425	1			T31	20		T236	10		T222	20
auto[0]	values[7]	values[3]	311	1			T180	20		T196	22		T237	4
auto[0]	values[7]	values[4]	339	1			T18	20		T238	12		T180	26
auto[0]	values[7]	values[5]	278	1			T98	6		T239	16		T240	14
auto[0]	values[7]	values[6]	268	1			T21	20		T31	21		T35	22
auto[0]	values[7]	values[7]	323	1			T29	34		T30	20		T155	23
auto[1]	values[0]	values[0]	5	1			T30	1		T155	1		T180	1
auto[1]	values[0]	values[1]	1	1			T241	1		-	-		-	-
auto[1]	values[0]	values[2]	5	1			T184	1		T185	1		T242	1
auto[1]	values[0]	values[3]	5	1			T34	2		T243	1		T244	2
auto[1]	values[0]	values[4]	4	1			T231	2		T245	2		-	-
auto[1]	values[0]	values[5]	9	1			T155	2		T208	1		T245	1
auto[1]	values[0]	values[6]	13	1			T30	1		T176	3		T177	2
auto[1]	values[0]	values[7]	10	1			T29	3		T246	1		T185	1
auto[1]	values[1]	values[0]	3	1			T247	1		T248	2		-	-
auto[1]	values[1]	values[1]	13	1			T31	4		T192	6		T249	1
auto[1]	values[1]	values[2]	8	1			T30	1		T177	1		T208	1
auto[1]	values[1]	values[3]	4	1			T26	1		T196	1		T250	2
auto[1]	values[1]	values[4]	7	1			T31	1		T251	4		T252	1
auto[1]	values[1]	values[5]	8	1			T208	2		T253	1		T245	4
auto[1]	values[1]	values[6]	8	1			T176	1		T159	1		T185	3
auto[1]	values[1]	values[7]	12	1			T31	4		T176	1		T254	3
auto[1]	values[2]	values[0]	7	1			T155	1		T196	2		T140	1
auto[1]	values[2]	values[1]	6	1			T255	4		T247	2		-	-
auto[1]	values[2]	values[2]	6	1			T242	3		T140	3		-	-
auto[1]	values[2]	values[3]	4	1			T175	1		T196	3		-	-
auto[1]	values[2]	values[4]	7	1			T26	2		T208	1		T185	1
auto[1]	values[2]	values[5]	4	1			T178	1		T163	2		T142	1
auto[1]	values[2]	values[6]	4	1			T246	2		T256	2		-	-
auto[1]	values[2]	values[7]	11	1			T175	1		T208	4		T257	2
auto[1]	values[3]	values[0]	2	1			T205	1		T258	1		-	-
auto[1]	values[3]	values[1]	3	1			T246	1		T259	2		-	-
auto[1]	values[3]	values[2]	5	1			T21	2		T29	1		T191	1
auto[1]	values[3]	values[3]	10	1			T177	2		T198	1		T199	3
auto[1]	values[3]	values[4]	5	1			T260	1		T242	3		T261	1
auto[1]	values[3]	values[5]	5	1			T140	1		T163	3		T262	1
auto[1]	values[3]	values[6]	1	1			T263	1		-	-		-	-
auto[1]	values[3]	values[7]	6	1			T35	1		T211	1		T208	2
auto[1]	values[4]	values[0]	7	1			T26	1		T32	1		T264	1
auto[1]	values[4]	values[1]	7	1			T195	1		T241	3		T265	1
auto[1]	values[4]	values[2]	4	1			T21	1		T266	1		T254	2
auto[1]	values[4]	values[3]	6	1			T195	2		T267	3		T268	1
auto[1]	values[4]	values[4]	3	1			T216	1		T247	2		-	-
auto[1]	values[4]	values[5]	2	1			T242	1		T258	1		-	-
auto[1]	values[4]	values[6]	14	1			T176	3		T226	3		T208	5
auto[1]	values[4]	values[7]	1	1			T195	1		-	-		-	-
auto[1]	values[5]	values[0]	10	1			T30	2		T155	2		T159	1
auto[1]	values[5]	values[1]	9	1			T269	1		T270	8		-	-
auto[1]	values[5]	values[2]	7	1			T207	1		T140	2		T271	2
auto[1]	values[5]	values[3]	5	1			T35	2		T176	2		T142	1
auto[1]	values[5]	values[5]	2	1			T272	1		T47	1		-	-
auto[1]	values[5]	values[7]	4	1			T161	1		T273	1		T262	2
auto[1]	values[6]	values[0]	3	1			T231	1		T244	1		T273	1
auto[1]	values[6]	values[1]	10	1			T33	2		T246	1		T274	1
auto[1]	values[6]	values[2]	5	1			T29	1		T275	2		T161	2
auto[1]	values[6]	values[3]	8	1			T16	1		T272	2		T191	1
auto[1]	values[6]	values[4]	3	1			T276	2		T254	1		-	-
auto[1]	values[6]	values[5]	1	1			T208	1		-	-		-	-
auto[1]	values[6]	values[6]	8	1			T16	3		T29	3		T264	1
auto[1]	values[6]	values[7]	5	1			T277	1		T255	2		T215	1
auto[1]	values[7]	values[0]	3	1			T195	1		T265	1		T142	1
auto[1]	values[7]	values[1]	2	1			T176	1		T177	1		-	-
auto[1]	values[7]	values[2]	8	1			T195	1		T278	2		T279	2
auto[1]	values[7]	values[3]	9	1			T196	1		T276	2		T247	2
auto[1]	values[7]	values[4]	2	1			T180	1		T163	1		-	-
auto[1]	values[7]	values[5]	4	1			T177	1		T195	1		T276	2
auto[1]	values[7]	values[6]	7	1			T177	1		T246	4		T280	1
auto[1]	values[7]	values[7]	6	1			T155	2		T159	4		-	-