Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1884

1

T4

1

T10

14

T11

4

auto[1]

1872

1

T4

2

T10

16

T11

4

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1947

1

T4

3

T14

10

T16

14

auto[1]

1809

1

T10

30

T11

8

T13

21

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3025

1

T4

3

T10

30

T11

8

auto[1]

731

1

T14

5

T16

7

T18

3

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	751	1			T4	2		T10	6		T11	2
valid[1]	733	1			T10	6		T13	4		T14	4
valid[2]	814	1			T10	4		T11	2		T13	2
valid[3]	724	1			T10	9		T11	3		T13	6
valid[4]	734	1			T4	1		T10	5		T11	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	110	1			T4	1		T25	1		T43	1
auto[0]	auto[0]	valid[0]	auto[1]	170	1			T10	5		T11	2		T13	2
auto[0]	auto[0]	valid[1]	auto[0]	125	1			T14	2		T18	2		T43	1
auto[0]	auto[0]	valid[1]	auto[1]	176	1			T10	1		T13	2		T88	1
auto[0]	auto[0]	valid[2]	auto[0]	118	1			T42	2		T29	2		T57	2
auto[0]	auto[0]	valid[2]	auto[1]	219	1			T10	2		T13	1		T88	7
auto[0]	auto[0]	valid[3]	auto[0]	116	1			T18	1		T43	1		T29	1
auto[0]	auto[0]	valid[3]	auto[1]	172	1			T10	3		T11	2		T13	6
auto[0]	auto[0]	valid[4]	auto[0]	126	1			T16	2		T25	2		T43	2
auto[0]	auto[0]	valid[4]	auto[1]	187	1			T10	3		T13	1		T88	3
auto[0]	auto[1]	valid[0]	auto[0]	135	1			T4	1		T14	1		T16	1
auto[0]	auto[1]	valid[0]	auto[1]	170	1			T10	1		T13	2		T88	5
auto[0]	auto[1]	valid[1]	auto[0]	131	1			T14	1		T16	2		T25	1
auto[0]	auto[1]	valid[1]	auto[1]	160	1			T10	5		T13	2		T88	5
auto[0]	auto[1]	valid[2]	auto[0]	133	1			T16	1		T25	2		T43	2
auto[0]	auto[1]	valid[2]	auto[1]	202	1			T10	2		T11	2		T13	1
auto[0]	auto[1]	valid[3]	auto[0]	104	1			T43	1		T31	1		T29	3
auto[0]	auto[1]	valid[3]	auto[1]	176	1			T10	6		T11	1		T18	2
auto[0]	auto[1]	valid[4]	auto[0]	118	1			T4	1		T14	1		T16	1
auto[0]	auto[1]	valid[4]	auto[1]	177	1			T10	2		T11	1		T13	4
auto[1]	auto[0]	valid[0]	auto[0]	83	1			T14	1		T18	2		T42	1
auto[1]	auto[0]	valid[1]	auto[0]	75	1			T25	1		T42	1		T31	1
auto[1]	auto[0]	valid[2]	auto[0]	72	1			T14	1		T25	1		T43	1
auto[1]	auto[0]	valid[3]	auto[0]	74	1			T16	1		T42	1		T179	1
auto[1]	auto[0]	valid[4]	auto[0]	61	1			T25	1		T43	1		T32	2
auto[1]	auto[1]	valid[0]	auto[0]	83	1			T14	1		T16	1		T43	1
auto[1]	auto[1]	valid[1]	auto[0]	66	1			T14	1		T16	1		T43	1
auto[1]	auto[1]	valid[2]	auto[0]	70	1			T43	1		T31	1		T29	1
auto[1]	auto[1]	valid[3]	auto[0]	82	1			T14	1		T16	2		T18	1
auto[1]	auto[1]	valid[4]	auto[0]	65	1			T16	2		T42	2		T32	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal