Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49140

1

T4

82

T14

314

T16

306

auto[1]

18651

1

T10

385

T11

8

T13

245

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49810

1

T4

52

T10

385

T11

8

auto[1]

17981

1

T4

30

T14

130

T16

118

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34819	1			T4	41		T10	183		T11	8
others[1]	5884	1			T4	4		T10	39		T13	10
others[2]	5690	1			T4	7		T10	25		T13	23
others[3]	6463	1			T4	7		T10	40		T13	23
interest[1]	3858	1			T4	9		T10	21		T13	12
interest[4]	22763	1			T4	24		T10	113		T11	8
interest[64]	11077	1			T4	14		T10	77		T13	38

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15978	1			T4	24		T14	90		T16	98
auto[0]	auto[0]	others[1]	2708	1			T4	2		T14	13		T16	10
auto[0]	auto[0]	others[2]	2639	1			T4	4		T14	17		T16	15
auto[0]	auto[0]	others[3]	3028	1			T4	5		T14	18		T16	28
auto[0]	auto[0]	interest[1]	1771	1			T4	6		T14	12		T16	12
auto[0]	auto[0]	interest[4]	10380	1			T4	14		T14	56		T16	55
auto[0]	auto[0]	interest[64]	5035	1			T4	11		T14	34		T16	25
auto[0]	auto[1]	others[0]	9701	1			T10	183		T11	8		T13	139
auto[0]	auto[1]	others[1]	1632	1			T10	39		T13	10		T14	2
auto[0]	auto[1]	others[2]	1531	1			T10	25		T13	23		T14	2
auto[0]	auto[1]	others[3]	1704	1			T10	40		T13	23		T14	5
auto[0]	auto[1]	interest[1]	1054	1			T10	21		T13	12		T14	1
auto[0]	auto[1]	interest[4]	6451	1			T10	113		T11	8		T13	91
auto[0]	auto[1]	interest[64]	3029	1			T10	77		T13	38		T14	8
auto[1]	auto[0]	others[0]	9140	1			T4	17		T14	55		T16	63
auto[1]	auto[0]	others[1]	1544	1			T4	2		T14	20		T16	8
auto[1]	auto[0]	others[2]	1520	1			T4	3		T14	13		T16	17
auto[1]	auto[0]	others[3]	1731	1			T4	2		T14	16		T16	8
auto[1]	auto[0]	interest[1]	1033	1			T4	3		T14	7		T16	7
auto[1]	auto[0]	interest[4]	5932	1			T4	10		T14	29		T16	44
auto[1]	auto[0]	interest[64]	3013	1			T4	3		T14	19		T16	15

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal