Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	853	1			T29	10		T32	17		T61	17
all_values[1]	853	1			T29	10		T32	17		T61	17
all_values[2]	853	1			T29	10		T32	17		T61	17
all_values[3]	853	1			T29	10		T32	17		T61	17
all_values[4]	853	1			T29	10		T32	17		T61	17
all_values[5]	853	1			T29	10		T32	17		T61	17
all_values[6]	853	1			T29	10		T32	17		T61	17
all_values[7]	853	1			T29	10		T32	17		T61	17

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3699

1

T29

41

T32

78

T61

79

auto[1]

3125

1

T29

39

T32

58

T61

57

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2655

1

T29

25

T32

49

T61

54

auto[1]

4169

1

T29

55

T32

87

T61

82

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3797

1

T29

41

T32

70

T61

72

auto[1]

3027

1

T29

39

T32

66

T61

64

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	165	1			T29	4		T61	3		T173	2
all_values[0]	auto[0]	auto[0]	auto[1]	64	1			T32	4		T61	1		T173	5
all_values[0]	auto[0]	auto[1]	auto[0]	164	1			T29	3		T32	3		T61	7
all_values[0]	auto[0]	auto[1]	auto[1]	87	1			T32	1		T61	1		T173	1
all_values[0]	auto[1]	auto[0]	auto[1]	199	1			T32	6		T61	4		T173	7
all_values[0]	auto[1]	auto[1]	auto[1]	174	1			T29	3		T32	3		T61	1
all_values[1]	auto[0]	auto[0]	auto[0]	199	1			T29	3		T32	5		T61	4
all_values[1]	auto[0]	auto[0]	auto[1]	85	1			T29	1		T32	1		T61	2
all_values[1]	auto[0]	auto[1]	auto[0]	121	1			T32	2		T61	2		T173	2
all_values[1]	auto[0]	auto[1]	auto[1]	81	1			T29	2		T61	2		T173	4
all_values[1]	auto[1]	auto[0]	auto[1]	210	1			T32	4		T61	5		T173	5
all_values[1]	auto[1]	auto[1]	auto[1]	157	1			T29	4		T32	5		T61	2
all_values[2]	auto[0]	auto[0]	auto[0]	178	1			T29	1		T32	5		T173	3
all_values[2]	auto[0]	auto[0]	auto[1]	75	1			T29	2		T32	1		T61	5
all_values[2]	auto[0]	auto[1]	auto[0]	150	1			T29	3		T32	6		T61	2
all_values[2]	auto[0]	auto[1]	auto[1]	81	1			T32	1		T173	1		T155	1
all_values[2]	auto[1]	auto[0]	auto[1]	204	1			T29	3		T32	4		T61	3
all_values[2]	auto[1]	auto[1]	auto[1]	165	1			T29	1		T61	7		T173	4
all_values[3]	auto[0]	auto[0]	auto[0]	166	1			T29	1		T32	2		T61	4
all_values[3]	auto[0]	auto[0]	auto[1]	90	1			T29	3		T32	4		T173	2
all_values[3]	auto[0]	auto[1]	auto[0]	142	1			T32	3		T61	3		T173	2
all_values[3]	auto[0]	auto[1]	auto[1]	80	1			T29	1		T32	1		T61	1
all_values[3]	auto[1]	auto[0]	auto[1]	209	1			T29	2		T32	5		T61	5
all_values[3]	auto[1]	auto[1]	auto[1]	166	1			T29	3		T32	2		T61	4
all_values[4]	auto[0]	auto[0]	auto[0]	176	1			T29	2		T32	2		T61	6
all_values[4]	auto[0]	auto[0]	auto[1]	91	1			T32	1		T61	1		T173	2
all_values[4]	auto[0]	auto[1]	auto[0]	129	1			T32	5		T173	2		T154	2
all_values[4]	auto[0]	auto[1]	auto[1]	69	1			T29	1		T173	2		T154	1
all_values[4]	auto[1]	auto[0]	auto[1]	214	1			T29	5		T32	5		T61	6
all_values[4]	auto[1]	auto[1]	auto[1]	174	1			T29	2		T32	4		T61	4
all_values[5]	auto[0]	auto[0]	auto[0]	243	1			T29	2		T32	4		T61	5
all_values[5]	auto[0]	auto[1]	auto[0]	211	1			T29	3		T32	3		T61	3
all_values[5]	auto[1]	auto[0]	auto[1]	219	1			T29	4		T32	5		T61	6
all_values[5]	auto[1]	auto[1]	auto[1]	180	1			T29	1		T32	5		T61	3
all_values[6]	auto[0]	auto[0]	auto[0]	171	1			T29	1		T32	1		T61	6
all_values[6]	auto[0]	auto[0]	auto[1]	91	1			T29	1		T32	2		T61	2
all_values[6]	auto[0]	auto[1]	auto[0]	122	1			T29	2		T32	3		T61	4
all_values[6]	auto[0]	auto[1]	auto[1]	90	1			T29	1		T32	1		T173	1
all_values[6]	auto[1]	auto[0]	auto[1]	212	1			T29	3		T32	7		T61	2
all_values[6]	auto[1]	auto[1]	auto[1]	167	1			T29	2		T32	3		T61	3
all_values[7]	auto[0]	auto[0]	auto[0]	174	1			T32	4		T61	3		T173	3
all_values[7]	auto[0]	auto[0]	auto[1]	70	1			T29	1		T32	4		T61	1
all_values[7]	auto[0]	auto[1]	auto[0]	144	1			T32	1		T61	2		T173	4
all_values[7]	auto[0]	auto[1]	auto[1]	88	1			T29	3		T61	2		T173	1
all_values[7]	auto[1]	auto[0]	auto[1]	194	1			T29	2		T32	2		T61	5
all_values[7]	auto[1]	auto[1]	auto[1]	183	1			T29	4		T32	6		T61	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal