Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2683189	1			T1	1		T2	789		T3	132
all_values[1]	2683189	1			T1	1		T2	789		T3	132
all_values[2]	2683189	1			T1	1		T2	789		T3	132
all_values[3]	2683189	1			T1	1		T2	789		T3	132
all_values[4]	2683189	1			T1	1		T2	789		T3	132
all_values[5]	2683189	1			T1	1		T2	789		T3	132
all_values[6]	2683189	1			T1	1		T2	789		T3	132
all_values[7]	2683189	1			T1	1		T2	789		T3	132

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20979788

1

T1

8

T2

6312

T3

1056

auto[1]

485724

1

T4

62

T22

214988

T28

60

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21440722

1

T1

8

T2

6312

T3

1056

auto[1]

24790

1

T4

302

T11

240

T13

329

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2597020	1			T1	1		T2	789		T3	132
all_values[0]	auto[0]	auto[1]	12989	1			T4	211		T11	131		T13	172
all_values[0]	auto[1]	auto[0]	72480	1			T4	3		T22	53500		T28	5
all_values[0]	auto[1]	auto[1]	700	1			T4	5		T22	246		T28	1
all_values[1]	auto[0]	auto[0]	2655289	1			T1	1		T2	789		T3	132
all_values[1]	auto[0]	auto[1]	6276	1			T4	39		T11	109		T13	116
all_values[1]	auto[1]	auto[0]	21357	1			T4	3		T28	4		T46	7
all_values[1]	auto[1]	auto[1]	267	1			T4	5		T28	1		T46	2
all_values[2]	auto[0]	auto[0]	2597988	1			T1	1		T2	789		T3	132
all_values[2]	auto[0]	auto[1]	2440	1			T4	4		T13	41		T15	60
all_values[2]	auto[1]	auto[0]	82528	1			T4	2		T22	53746		T28	8
all_values[2]	auto[1]	auto[1]	233	1			T4	3		T28	1		T46	1
all_values[3]	auto[0]	auto[0]	2623446	1			T1	1		T2	789		T3	132
all_values[3]	auto[0]	auto[1]	188	1			T4	2		T32	1		T22	4
all_values[3]	auto[1]	auto[0]	59364	1			T4	5		T28	4		T46	6
all_values[3]	auto[1]	auto[1]	191	1			T4	1		T28	8		T46	6
all_values[4]	auto[0]	auto[0]	2614376	1			T1	1		T2	789		T3	132
all_values[4]	auto[0]	auto[1]	178	1			T4	3		T22	1		T28	2
all_values[4]	auto[1]	auto[0]	68451	1			T4	6		T22	53746		T28	5
all_values[4]	auto[1]	auto[1]	184	1			T4	5		T28	5		T46	3
all_values[5]	auto[0]	auto[0]	2603900	1			T1	1		T2	789		T3	132
all_values[5]	auto[0]	auto[1]	252	1			T4	4		T226	4		T28	1
all_values[5]	auto[1]	auto[0]	78865	1			T4	4		T22	53746		T28	6
all_values[5]	auto[1]	auto[1]	172	1			T4	3		T22	1		T28	2
all_values[6]	auto[0]	auto[0]	2654866	1			T1	1		T2	789		T3	132
all_values[6]	auto[0]	auto[1]	172	1			T4	5		T28	4		T46	6
all_values[6]	auto[1]	auto[0]	27980	1			T4	4		T28	2		T46	6
all_values[6]	auto[1]	auto[1]	171	1			T4	3		T22	1		T28	3
all_values[7]	auto[0]	auto[0]	2610227	1			T1	1		T2	789		T3	132
all_values[7]	auto[0]	auto[1]	181	1			T4	5		T28	2		T46	2
all_values[7]	auto[1]	auto[0]	72585	1			T4	6		T22	1		T28	3
all_values[7]	auto[1]	auto[1]	196	1			T4	4		T22	1		T28	2