Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	29568	1			T2	29		T4	226		T6	6
auto[SpiFlashAddrCfg]	6385	1			T2	6		T4	62		T6	2
auto[SpiFlashAddr3b]	7799	1			T2	4		T4	65		T6	6
auto[SpiFlashAddr4b]	6511	1			T2	8		T4	56		T6	6

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27708

1

T2

35

T4

198

T6

20

auto[1]

22555

1

T2

12

T4

211

T11

92

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26432

1

T2

30

T4

200

T6

14

auto[1]

23831

1

T2

17

T4

209

T6

6

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	33446	1			T2	30		T4	257		T6	6
values[1]	927	1			T2	1		T4	14		T11	1
values[2]	1247	1			T4	13		T6	2		T11	7
values[3]	1218	1			T2	4		T4	7		T11	8
values[4]	1267	1			T4	11		T11	12		T13	13
values[5]	1238	1			T4	9		T6	2		T11	12
values[6]	1250	1			T4	13		T11	11		T13	6
values[7]	1276	1			T4	13		T11	9		T13	11
values[8]	8394	1			T2	12		T4	72		T6	10

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24971

1

T4

409

T6

20

T9

12

auto[1]

25292

1

T2

47

T14

183

T15

293

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

48477

1

T2

46

T4

397

T6

20

write

1786

1

T2

1

T4

12

T11

11

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

16954

1

T2

22

T4

149

T6

2

valids[0x1]

33309

1

T2

25

T4

260

T6

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1336	1			T2	4		T4	9		T6	2
internal_process_ops[0x5a]	1326	1			T4	13		T6	4		T11	10
internal_process_ops[0x05]	17754	1			T2	11		T4	137		T11	59
internal_process_ops[0x35]	1274	1			T4	10		T11	8		T13	11
internal_process_ops[0x15]	1357	1			T2	1		T4	12		T6	4
internal_process_ops[0x03]	896	1			T4	10		T6	4		T11	6
internal_process_ops[0x0b]	864	1			T2	1		T4	9		T6	2
internal_process_ops[0x3b]	935	1			T4	15		T6	2		T11	13
internal_process_ops[0x6b]	910	1			T4	11		T9	4		T11	8
internal_process_ops[0xbb]	905	1			T2	1		T4	18		T11	16
internal_process_ops[0xeb]	927	1			T4	12		T11	4		T13	13

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49358

1

T2

47

T4

402

T6

20

auto[1]

905

1

T4

7

T11

6

T13

6

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48486

1

T2

45

T4

393

T6

20

auto[1]

1777

1

T2

2

T4

16

T11

8

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

7973

1

T4

103

T6

6

T11

104

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5418

1

T4

123

T11

20

T13

40

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1719

1

T4

24

T6

2

T11

21

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1587

1

T4

34

T11

19

T13

33

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2114

1

T4

32

T6

6

T9

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1871

1

T4

28

T11

25

T13

33

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1894

1

T4

32

T6

6

T9

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1560

1

T4

21

T11

22

T13

31

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

61

1

T24

2

T31

1

T176

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

63

1

T11

2

T13

2

T27

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

54

1

T11

1

T13

1

T144

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

60

1

T24

1

T26

1

T27

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

72

1

T24

2

T27

1

T156

6

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

40

1

T4

2

T11

1

T13

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

38

1

T11

3

T23

3

T24

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

48

1

T4

2

T11

1

T13

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

50

1

T4

1

T13

1

T23

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

55

1

T4

2

T11

2

T27

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

64

1

T4

2

T11

1

T23

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

49

1

T23

1

T28

1

T156

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

46

1

T4

2

T23

1

T26

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

41

1

T13

1

T24

2

T27

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

37

1

T23

1

T24

1

T27

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

57

1

T4

1

T24

2

T27

3

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8799

1

T2

26

T14

48

T15

64

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6886

1

T2

3

T14

31

T15

82

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1349

1

T2

4

T14

27

T15

26

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1290

1

T2

2

T14

11

T15

16

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1664

1

T2

2

T14

12

T15

14

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1704

1

T2

2

T14

15

T15

28

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1269

1

T2

2

T14

12

T15

22

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1380

1

T2

5

T14

12

T15

25

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

88

1

T15

4

T22

2

T30

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

64

1

T14

1

T15

1

T224

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

55

1

T14

1

T15

3

T22

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

47

1

T14

2

T69

2

T85

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

51

1

T14

2

T15

3

T68

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

71

1

T15

1

T68

4

T30

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

70

1

T22

2

T224

2

T225

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

50

1

T15

2

T69

2

T225

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

53

1

T14

2

T68

1

T69

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

60

1

T14

1

T15

1

T28

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

52

1

T14

1

T15

1

T22

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

63

1

T14

1

T22

3

T68

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

43

1

T2

1

T85

2

T141

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

69

1

T22

1

T68

1

T85

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

47

1

T14

3

T68

1

T69

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

68

1

T14

1

T225

1

T30

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3493	1			T4	61		T11	42		T13	59
auto[0]	values[0]	valids[0x1]	12170	1			T4	196		T6	6		T11	111
auto[0]	values[1]	valids[0x1]	451	1			T4	14		T11	1		T13	6
auto[0]	values[2]	valids[0x0]	458	1			T4	11		T11	4		T13	11
auto[0]	values[2]	valids[0x1]	221	1			T4	2		T6	2		T11	3
auto[0]	values[3]	valids[0x0]	458	1			T4	5		T11	5		T13	4
auto[0]	values[3]	valids[0x1]	239	1			T4	2		T11	3		T13	6
auto[0]	values[4]	valids[0x0]	446	1			T4	6		T11	9		T13	10
auto[0]	values[4]	valids[0x1]	271	1			T4	5		T11	3		T13	3
auto[0]	values[5]	valids[0x0]	484	1			T4	4		T6	2		T11	6
auto[0]	values[5]	valids[0x1]	224	1			T4	5		T11	6		T13	7
auto[0]	values[6]	valids[0x0]	456	1			T4	9		T11	8		T13	4
auto[0]	values[6]	valids[0x1]	220	1			T4	4		T11	3		T13	2
auto[0]	values[7]	valids[0x0]	461	1			T4	10		T11	7		T13	6
auto[0]	values[7]	valids[0x1]	253	1			T4	3		T11	2		T13	5
auto[0]	values[8]	valids[0x0]	2915	1			T4	43		T9	4		T11	42
auto[0]	values[8]	valids[0x1]	1751	1			T4	29		T6	10		T9	8
auto[1]	values[0]	valids[0x0]	3652	1			T2	12		T14	28		T15	52
auto[1]	values[0]	valids[0x1]	14131	1			T2	18		T14	75		T15	117
auto[1]	values[1]	valids[0x1]	476	1			T2	1		T14	11		T15	17
auto[1]	values[2]	valids[0x0]	347	1			T14	4		T15	8		T32	1
auto[1]	values[2]	valids[0x1]	221	1			T14	1		T15	2		T22	2
auto[1]	values[3]	valids[0x0]	310	1			T2	3		T14	3		T15	8
auto[1]	values[3]	valids[0x1]	211	1			T2	1		T14	1		T15	2
auto[1]	values[4]	valids[0x0]	326	1			T14	7		T15	2		T22	3
auto[1]	values[4]	valids[0x1]	224	1			T15	2		T22	4		T68	2
auto[1]	values[5]	valids[0x0]	290	1			T14	2		T68	3		T85	2
auto[1]	values[5]	valids[0x1]	240	1			T14	3		T15	4		T22	7
auto[1]	values[6]	valids[0x0]	341	1			T14	3		T15	11		T22	3
auto[1]	values[6]	valids[0x1]	233	1			T14	1		T15	1		T22	7
auto[1]	values[7]	valids[0x0]	379	1			T14	6		T15	4		T22	7
auto[1]	values[7]	valids[0x1]	183	1			T14	4		T15	1		T22	3
auto[1]	values[8]	valids[0x0]	2138	1			T2	7		T14	20		T15	30
auto[1]	values[8]	valids[0x1]	1590	1			T2	5		T14	14		T15	32