Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2877789

1

T2

1643

T4

23255

T6

1281

auto[1]

16333

1

T2

7

T4

129

T11

58

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

851945

1

T2

13

T4

85

T6

1

auto[1]

2042177

1

T2

1637

T4

23299

T6

1280

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	595648	1			T2	2		T4	2313		T6	1281
auto[524288:1048575]	322024	1			T4	3657		T11	2331		T12	185
auto[1048576:1572863]	341269	1			T4	18		T9	242		T11	2298
auto[1572864:2097151]	303003	1			T2	1174		T4	2986		T11	3030
auto[2097152:2621439]	310425	1			T2	3		T4	3302		T9	469
auto[2621440:3145727]	364062	1			T4	134		T9	151		T11	525
auto[3145728:3670015]	330947	1			T2	1		T4	405		T9	713
auto[3670016:4194303]	326744	1			T2	470		T4	10569		T9	7

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2060536

1

T2

1647

T4

23376

T6

1281

auto[1]

833586

1

T2

3

T4

8

T9

2246

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2513987

1

T2

472

T4

18000

T6

1281

auto[1]

380135

1

T2

1178

T4

5384

T11

5745

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	193673	1			T2	1		T4	2		T6	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	344390	1			T4	1		T6	1280		T11	2823
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	76741	1			T4	7		T11	3		T12	185
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	199357	1			T4	3602		T11	1		T13	3721
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	121890	1			T4	8		T9	242		T11	3
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	161656	1			T4	5		T11	2270		T13	601
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	81976	1			T4	15		T11	4		T12	27
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	166302	1			T4	2925		T11	128		T13	784
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	83794	1			T2	3		T4	2		T9	469
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	175097	1			T4	769		T13	2688		T14	3103
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	105038	1			T4	3		T9	151		T11	5
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	218602	1			T4	129		T11	517		T13	3
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	84885	1			T2	1		T4	7		T9	713
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	205739	1			T4	129		T11	2856		T13	3222
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	97056	1			T2	5		T4	4		T9	7
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	184145	1			T2	455		T4	10303		T13	2409
auto[0]	auto[1]	auto[0:524287]	auto[0]	250	1			T2	1		T4	1		T11	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	54495	1			T4	2303		T11	516		T13	2843
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	360	1			T4	9		T11	3		T14	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	43208	1			T4	2		T11	2296		T22	256
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1284	1			T11	2		T135	3		T23	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	54537	1			T11	6		T23	2158		T69	1350
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	744	1			T11	3		T13	3		T24	4
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	52149	1			T2	1174		T11	2895		T13	5836
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	440	1			T4	7		T22	5		T24	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	49418	1			T4	2504		T22	1		T85	768
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	542	1			T11	1		T13	5		T37	9
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	37778	1			T11	1		T13	665		T23	384
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	344	1			T4	2		T11	4		T13	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	38041	1			T4	257		T14	512		T22	3957
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1148	1			T4	2		T37	10		T135	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	42710	1			T2	3		T4	257		T26	1977
auto[1]	auto[0]	auto[0:524287]	auto[0]	222	1			T4	1		T11	1		T13	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	2258	1			T4	2		T11	1		T13	4
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	182	1			T4	1		T11	1		T14	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1673	1			T4	29		T11	24		T14	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	166	1			T4	1		T11	1		T13	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1385	1			T4	4		T11	9		T15	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	174	1			T4	3		T13	1		T15	4
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1408	1			T4	43		T13	3		T15	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	163	1			T4	1		T13	2		T14	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1238	1			T4	1		T13	6		T14	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	198	1			T4	1		T13	1		T14	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1534	1			T4	1		T13	4		T14	4
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	175	1			T4	1		T11	1		T13	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1434	1			T11	4		T14	1		T15	4
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	163	1			T2	2		T13	1		T15	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1273	1			T2	5		T13	1		T15	3
auto[1]	auto[1]	auto[0:524287]	auto[0]	45	1			T4	1		T11	1		T13	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	315	1			T4	2		T11	4		T13	7
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	48	1			T4	2		T11	1		T23	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	455	1			T4	5		T11	2		T68	15
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	42	1			T11	1		T31	2		T144	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	309	1			T11	6		T31	21		T144	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	26	1			T13	2		T68	1		T27	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	224	1			T13	13		T68	2		T27	6
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	38	1			T4	2		T22	1		T224	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	237	1			T4	16		T224	37		T28	5
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	50	1			T11	1		T68	1		T225	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	320	1			T31	41		T255	32		T155	43
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	44	1			T4	1		T22	4		T24	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	285	1			T4	8		T22	1		T24	19
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	44	1			T4	1		T85	1		T141	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	205	1			T4	2		T85	1		T141	4

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1669767	1			T2	463		T4	17909		T6	1281
auto[0]	auto[0]	auto[1]	830574	1			T2	2		T4	2		T9	2246
auto[0]	auto[1]	auto[0]	374759	1			T2	1178		T4	5341		T11	5729
auto[0]	auto[1]	auto[1]	2689	1			T4	3		T13	1		T37	6
auto[1]	auto[0]	auto[0]	13381	1			T2	6		T4	87		T11	40
auto[1]	auto[0]	auto[1]	265	1			T2	1		T4	2		T11	2
auto[1]	auto[1]	auto[0]	2629	1			T4	39		T11	14		T13	22
auto[1]	auto[1]	auto[1]	58	1			T4	1		T11	2		T13	2