Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14128

1

T4

198

T6

20

T9

12

auto[1]

10843

1

T4

211

T11

92

T13

139

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2697	1			T11	20		T13	49		T23	20
values[1]	2616	1			T4	121		T11	78		T13	29
values[2]	3447	1			T4	73		T11	69		T13	50
values[3]	2946	1			T4	55		T11	20		T12	4
values[4]	2893	1			T4	20		T11	20		T13	42
values[5]	3611	1			T11	71		T13	40		T18	10
values[6]	3236	1			T4	99		T6	20		T9	12
values[7]	3525	1			T4	41		T13	44		T147	8

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3114	1			T6	20		T13	28		T23	47
values[1]	3125	1			T4	21		T11	58		T12	4
values[2]	3520	1			T4	58		T13	53		T135	12
values[3]	2719	1			T4	25		T11	20		T13	41
values[4]	3445	1			T4	20		T9	12		T11	77
values[5]	3155	1			T4	70		T11	21		T13	45
values[6]	2457	1			T4	92		T11	40		T13	68
values[7]	3436	1			T4	123		T11	62		T13	45

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	146	1			T24	15		T143	10		T144	16
auto[0]	values[0]	values[1]	202	1			T122	14		T208	14		T180	32
auto[0]	values[0]	values[2]	278	1			T13	12		T30	38		T143	39
auto[0]	values[0]	values[3]	140	1			T23	8		T28	16		T149	16
auto[0]	values[0]	values[4]	161	1			T177	10		T208	10		T263	8
auto[0]	values[0]	values[5]	176	1			T122	13		T264	10		T265	6
auto[0]	values[0]	values[6]	189	1			T11	7		T155	10		T186	9
auto[0]	values[0]	values[7]	175	1			T13	14		T144	25		T182	11
auto[0]	values[1]	values[0]	242	1			T24	26		T176	10		T145	11
auto[0]	values[1]	values[1]	226	1			T11	44		T38	8		T24	26
auto[0]	values[1]	values[2]	224	1			T4	12		T13	28		T28	20
auto[0]	values[1]	values[3]	127	1			T4	9		T154	18		T174	10
auto[0]	values[1]	values[4]	207	1			T24	7		T31	75		T149	9
auto[0]	values[1]	values[5]	192	1			T39	4		T27	7		T31	46
auto[0]	values[1]	values[6]	102	1			T149	9		T162	10		T182	8
auto[0]	values[1]	values[7]	159	1			T4	12		T11	13		T24	8
auto[0]	values[2]	values[0]	247	1			T13	12		T83	14		T28	7
auto[0]	values[2]	values[1]	313	1			T4	10		T37	8		T31	87
auto[0]	values[2]	values[2]	228	1			T23	8		T166	8		T143	14
auto[0]	values[2]	values[3]	257	1			T170	18		T143	21		T20	6
auto[0]	values[2]	values[4]	259	1			T11	23		T144	9		T155	27
auto[0]	values[2]	values[5]	284	1			T4	12		T13	13		T158	12
auto[0]	values[2]	values[6]	182	1			T11	10		T24	12		T156	14
auto[0]	values[2]	values[7]	217	1			T4	14		T11	7		T183	10
auto[0]	values[3]	values[0]	192	1			T23	9		T31	9		T149	9
auto[0]	values[3]	values[1]	230	1			T12	4		T27	27		T28	12
auto[0]	values[3]	values[2]	221	1			T4	12		T156	9		T30	12
auto[0]	values[3]	values[3]	255	1			T122	11		T180	9		T266	6
auto[0]	values[3]	values[4]	183	1			T23	22		T208	14		T152	24
auto[0]	values[3]	values[5]	166	1			T4	7		T176	18		T174	13
auto[0]	values[3]	values[6]	209	1			T13	18		T24	8		T27	12
auto[0]	values[3]	values[7]	216	1			T11	15		T13	13		T144	25
auto[0]	values[4]	values[0]	196	1			T23	8		T143	12		T208	11
auto[0]	values[4]	values[1]	136	1			T24	14		T175	6		T28	11
auto[0]	values[4]	values[2]	168	1			T164	4		T156	13		T143	7
auto[0]	values[4]	values[3]	250	1			T11	12		T17	10		T267	22
auto[0]	values[4]	values[4]	387	1			T4	8		T24	15		T28	77
auto[0]	values[4]	values[5]	220	1			T23	17		T115	2		T149	9
auto[0]	values[4]	values[6]	209	1			T13	18		T177	13		T180	9
auto[0]	values[4]	values[7]	73	1			T27	10		T165	13		T182	8
auto[0]	values[5]	values[0]	237	1			T27	46		T179	18		T174	38
auto[0]	values[5]	values[1]	307	1			T13	11		T99	2		T24	41
auto[0]	values[5]	values[2]	230	1			T159	6		T75	6		T183	8
auto[0]	values[5]	values[3]	139	1			T13	13		T184	10		T155	28
auto[0]	values[5]	values[4]	192	1			T11	42		T28	11		T165	38
auto[0]	values[5]	values[5]	368	1			T11	13		T24	15		T27	9
auto[0]	values[5]	values[6]	118	1			T30	21		T180	31		T210	9
auto[0]	values[5]	values[7]	378	1			T27	21		T261	20		T143	11
auto[0]	values[6]	values[0]	317	1			T6	20		T27	12		T177	34
auto[0]	values[6]	values[1]	210	1			T13	21		T144	10		T155	22
auto[0]	values[6]	values[2]	271	1			T135	12		T116	10		T167	4
auto[0]	values[6]	values[3]	195	1			T23	7		T268	12		T31	22
auto[0]	values[6]	values[4]	240	1			T9	12		T23	14		T77	12
auto[0]	values[6]	values[5]	204	1			T4	13		T156	13		T148	10
auto[0]	values[6]	values[6]	144	1			T4	43		T23	13		T26	12
auto[0]	values[6]	values[7]	223	1			T4	19		T187	24		T161	8
auto[0]	values[7]	values[0]	293	1			T26	12		T155	100		T186	12
auto[0]	values[7]	values[1]	257	1			T24	13		T143	16		T155	15
auto[0]	values[7]	values[2]	243	1			T24	9		T169	12		T165	31
auto[0]	values[7]	values[3]	197	1			T13	12		T149	10		T155	39
auto[0]	values[7]	values[4]	158	1			T178	4		T119	6		T31	26
auto[0]	values[7]	values[5]	210	1			T13	7		T27	18		T155	8
auto[0]	values[7]	values[6]	357	1			T4	27		T24	14		T27	11
auto[0]	values[7]	values[7]	396	1			T147	8		T23	10		T27	6
auto[1]	values[0]	values[0]	79	1			T24	5		T143	10		T144	7
auto[1]	values[0]	values[1]	211	1			T29	18		T122	6		T208	6
auto[1]	values[0]	values[2]	265	1			T13	12		T30	9		T143	9
auto[1]	values[0]	values[3]	134	1			T23	12		T28	4		T149	7
auto[1]	values[0]	values[4]	195	1			T177	10		T208	13		T269	13
auto[1]	values[0]	values[5]	51	1			T122	7		T203	6		T239	9
auto[1]	values[0]	values[6]	133	1			T11	13		T155	10		T186	11
auto[1]	values[0]	values[7]	162	1			T13	11		T144	23		T182	9
auto[1]	values[1]	values[0]	128	1			T24	5		T176	62		T145	11
auto[1]	values[1]	values[1]	70	1			T11	14		T24	3		T180	14
auto[1]	values[1]	values[2]	241	1			T4	11		T13	1		T28	22
auto[1]	values[1]	values[3]	106	1			T4	16		T174	10		T180	6
auto[1]	values[1]	values[4]	191	1			T24	13		T31	28		T149	14
auto[1]	values[1]	values[5]	101	1			T27	13		T31	10		T151	5
auto[1]	values[1]	values[6]	127	1			T149	11		T162	10		T182	47
auto[1]	values[1]	values[7]	173	1			T4	61		T11	7		T24	12
auto[1]	values[2]	values[0]	155	1			T13	16		T28	13		T30	8
auto[1]	values[2]	values[1]	152	1			T4	11		T31	15		T174	12
auto[1]	values[2]	values[2]	189	1			T23	12		T143	9		T165	10
auto[1]	values[2]	values[3]	186	1			T143	9		T20	14		T270	8
auto[1]	values[2]	values[4]	307	1			T11	4		T144	11		T155	157
auto[1]	values[2]	values[5]	111	1			T4	13		T13	9		T30	10
auto[1]	values[2]	values[6]	93	1			T11	10		T24	8		T156	6
auto[1]	values[2]	values[7]	267	1			T4	13		T11	15		T76	10
auto[1]	values[3]	values[0]	134	1			T23	18		T31	11		T188	2
auto[1]	values[3]	values[1]	165	1			T27	14		T28	8		T144	7
auto[1]	values[3]	values[2]	323	1			T4	23		T156	11		T30	15
auto[1]	values[3]	values[3]	159	1			T122	30		T180	24		T196	8
auto[1]	values[3]	values[4]	136	1			T23	18		T244	18		T208	6
auto[1]	values[3]	values[5]	76	1			T4	13		T176	2		T174	7
auto[1]	values[3]	values[6]	88	1			T13	8		T24	12		T27	8
auto[1]	values[3]	values[7]	193	1			T11	5		T13	7		T144	7
auto[1]	values[4]	values[0]	159	1			T23	12		T143	8		T208	9
auto[1]	values[4]	values[1]	137	1			T24	10		T28	9		T156	9
auto[1]	values[4]	values[2]	133	1			T156	10		T143	13		T162	14
auto[1]	values[4]	values[3]	176	1			T11	8		T194	11		T124	18
auto[1]	values[4]	values[4]	174	1			T4	12		T24	5		T173	8
auto[1]	values[4]	values[5]	138	1			T23	9		T149	19		T145	4
auto[1]	values[4]	values[6]	176	1			T13	24		T177	10		T180	28
auto[1]	values[4]	values[7]	161	1			T27	52		T165	7		T182	12
auto[1]	values[5]	values[0]	199	1			T27	16		T174	4		T270	11
auto[1]	values[5]	values[1]	225	1			T13	9		T24	7		T143	12
auto[1]	values[5]	values[2]	178	1			T183	18		T177	6		T208	12
auto[1]	values[5]	values[3]	162	1			T13	7		T18	10		T155	56
auto[1]	values[5]	values[4]	156	1			T11	8		T28	10		T165	14
auto[1]	values[5]	values[5]	296	1			T11	8		T24	110		T27	11
auto[1]	values[5]	values[6]	50	1			T30	6		T180	9		T271	8
auto[1]	values[5]	values[7]	376	1			T27	6		T205	10		T143	29
auto[1]	values[6]	values[0]	196	1			T27	12		T177	8		T180	10
auto[1]	values[6]	values[1]	135	1			T13	10		T144	10		T155	28
auto[1]	values[6]	values[2]	136	1			T149	10		T165	8		T20	6
auto[1]	values[6]	values[3]	101	1			T23	13		T31	7		T144	7
auto[1]	values[6]	values[4]	262	1			T23	6		T31	38		T183	12
auto[1]	values[6]	values[5]	347	1			T4	12		T185	16		T156	150
auto[1]	values[6]	values[6]	126	1			T4	8		T23	7		T26	8
auto[1]	values[6]	values[7]	129	1			T4	4		T177	12		T186	16
auto[1]	values[7]	values[0]	194	1			T26	23		T155	14		T186	8
auto[1]	values[7]	values[1]	149	1			T24	11		T143	4		T155	5
auto[1]	values[7]	values[2]	192	1			T24	11		T169	66		T165	13
auto[1]	values[7]	values[3]	135	1			T13	9		T149	10		T155	48
auto[1]	values[7]	values[4]	237	1			T31	41		T20	44		T193	7
auto[1]	values[7]	values[5]	215	1			T13	16		T27	11		T155	30
auto[1]	values[7]	values[6]	154	1			T4	14		T24	8		T27	9
auto[1]	values[7]	values[7]	138	1			T23	10		T27	38		T30	3