Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2683189	1			T1	1		T2	789		T3	132
all_pins[1]	2683189	1			T1	1		T2	789		T3	132
all_pins[2]	2683189	1			T1	1		T2	789		T3	132
all_pins[3]	2683189	1			T1	1		T2	789		T3	132
all_pins[4]	2683189	1			T1	1		T2	789		T3	132
all_pins[5]	2683189	1			T1	1		T2	789		T3	132
all_pins[6]	2683189	1			T1	1		T2	789		T3	132
all_pins[7]	2683189	1			T1	1		T2	789		T3	132

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21434564	1			T1	8		T2	6312		T3	1056
values[0x1]	30948	1			T4	29		T22	864		T28	23
transitions[0x0=>0x1]	29837	1			T4	19		T22	863		T28	15
transitions[0x1=>0x0]	29853	1			T4	20		T22	863		T28	15

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2682436	1			T1	1		T2	789		T3	132
all_pins[0]	values[0x1]	753	1			T4	5		T22	265		T28	1
all_pins[0]	transitions[0x0=>0x1]	616	1			T4	4		T22	265		T28	1
all_pins[0]	transitions[0x1=>0x0]	149	1			T4	4		T28	1		T46	2
all_pins[1]	values[0x0]	2682903	1			T1	1		T2	789		T3	132
all_pins[1]	values[0x1]	286	1			T4	5		T28	1		T46	2
all_pins[1]	transitions[0x0=>0x1]	211	1			T4	3		T28	1		T46	1
all_pins[1]	transitions[0x1=>0x0]	162	1			T4	1		T28	1		T141	5
all_pins[2]	values[0x0]	2682952	1			T1	1		T2	789		T3	132
all_pins[2]	values[0x1]	237	1			T4	3		T28	1		T46	1
all_pins[2]	transitions[0x0=>0x1]	184	1			T4	2		T46	1		T141	4
all_pins[2]	transitions[0x1=>0x0]	138	1			T28	7		T46	6		T141	1
all_pins[3]	values[0x0]	2682998	1			T1	1		T2	789		T3	132
all_pins[3]	values[0x1]	191	1			T4	1		T28	8		T46	6
all_pins[3]	transitions[0x0=>0x1]	135	1			T28	4		T46	5		T141	2
all_pins[3]	transitions[0x1=>0x0]	128	1			T4	4		T28	1		T46	2
all_pins[4]	values[0x0]	2683005	1			T1	1		T2	789		T3	132
all_pins[4]	values[0x1]	184	1			T4	5		T28	5		T46	3
all_pins[4]	transitions[0x0=>0x1]	140	1			T4	4		T28	4		T46	2
all_pins[4]	transitions[0x1=>0x0]	1632	1			T4	2		T22	597		T28	1
all_pins[5]	values[0x0]	2681513	1			T1	1		T2	789		T3	132
all_pins[5]	values[0x1]	1676	1			T4	3		T22	597		T28	2
all_pins[5]	transitions[0x0=>0x1]	1051	1			T4	3		T22	597		T28	1
all_pins[5]	transitions[0x1=>0x0]	26800	1			T4	3		T22	1		T28	2
all_pins[6]	values[0x0]	2655764	1			T1	1		T2	789		T3	132
all_pins[6]	values[0x1]	27425	1			T4	3		T22	1		T28	3
all_pins[6]	transitions[0x0=>0x1]	27371	1			T4	1		T28	2		T46	2
all_pins[6]	transitions[0x1=>0x0]	142	1			T4	2		T28	1		T46	6
all_pins[7]	values[0x0]	2682993	1			T1	1		T2	789		T3	132
all_pins[7]	values[0x1]	196	1			T4	4		T22	1		T28	2
all_pins[7]	transitions[0x0=>0x1]	129	1			T4	2		T22	1		T28	2
all_pins[7]	transitions[0x1=>0x0]	702	1			T4	4		T22	265		T28	1