Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	375	1			T4	11		T9	8		T11	3
auto[ReadAddrCrossIntoMailbox]	288	1			T4	18		T11	7		T13	3
auto[ReadAddrCrossOutOfMailbox]	297	1			T4	13		T11	6		T13	3
auto[ReadAddrCrossAllMailbox]	167	1			T4	6		T11	3		T13	2
auto[ReadAddrOutsideMailbox]	2964	1			T4	27		T6	8		T9	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1971

1

T4

42

T6

4

T9

6

auto[1]

2120

1

T4

33

T6

4

T9

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	669	1			T4	10		T6	4		T11	6
read_ops[0x0b]	648	1			T4	9		T6	2		T9	8
read_ops[0x3b]	706	1			T4	15		T6	2		T11	13
read_ops[0x6b]	705	1			T4	11		T9	4		T11	8
read_ops[0xbb]	659	1			T4	18		T11	16		T13	8
read_ops[0xeb]	704	1			T4	12		T11	4		T13	13

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T24	2		T27	2		T179	3
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T4	1		T23	1		T179	3
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T4	2		T144	2		T122	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T4	1		T11	1		T24	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T4	3		T23	2		T156	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T11	2		T13	1		T24	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T4	1		T11	1		T177	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T24	1		T30	2		T171	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	228	1			T4	1		T6	2		T13	6
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	236	1			T4	1		T6	2		T11	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T4	2		T9	4		T13	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T9	4		T13	1		T77	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T27	1		T28	1		T268	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T11	1		T268	1		T144	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T4	1		T23	1		T27	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T13	1		T30	2		T143	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T4	2		T23	1		T24	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	10	1			T27	1		T28	1		T30	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	225	1			T4	4		T6	1		T11	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	243	1			T6	1		T11	5		T13	6
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T4	1		T11	1		T23	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T4	2		T27	1		T179	4
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	14	1			T4	1		T176	1		T122	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T4	3		T11	1		T13	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T11	1		T116	1		T149	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	40	1			T4	2		T13	1		T24	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T149	2		T165	1		T180	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T4	1		T30	1		T122	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	246	1			T4	3		T6	1		T11	7
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	265	1			T4	2		T6	1		T11	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T4	1		T11	1		T31	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	41	1			T4	1		T11	1		T27	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T4	5		T11	1		T174	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T4	1		T13	1		T24	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T11	1		T24	3		T30	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T4	1		T23	1		T24	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T11	1		T174	1		T199	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T13	1		T23	1		T143	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	253	1			T4	2		T9	2		T12	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	265	1			T9	2		T11	3		T12	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T4	1		T23	2		T77	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T4	1		T24	1		T27	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T4	2		T174	1		T171	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T4	1		T11	3		T24	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T4	2		T11	1		T27	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T4	2		T31	1		T143	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T4	1		T11	1		T27	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T4	1		T23	2		T183	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	229	1			T4	2		T11	3		T13	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	248	1			T4	5		T11	8		T13	6
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	23	1			T77	1		T30	1		T166	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T4	1		T27	2		T77	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T4	1		T23	1		T268	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T4	1		T13	1		T27	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T4	1		T268	1		T144	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T4	1		T11	1		T27	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	9	1			T13	1		T176	1		T183	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T23	1		T24	1		T28	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	262	1			T4	3		T11	2		T13	6
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	264	1			T4	4		T11	1		T13	5