Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.95	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	3	125	97.66

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	3	125	97.66	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2616	1			T4	20		T6	20		T11	68
values[1]	2590	1			T4	35		T11	40		T12	4
values[2]	3709	1			T4	46		T11	52		T13	51
values[3]	3219	1			T4	41		T11	27		T13	44
values[4]	3338	1			T4	169		T13	43		T17	10
values[5]	3297	1			T13	66		T99	2		T24	86
values[6]	2899	1			T4	25		T13	20		T23	40
values[7]	3303	1			T4	73		T9	12		T11	91

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3388	1			T4	27		T11	48		T13	70
values[1]	3009	1			T4	129		T9	12		T13	31
values[2]	2908	1			T11	22		T13	51		T17	10
values[3]	3317	1			T4	138		T11	21		T23	27
values[4]	3010	1			T11	60		T13	65		T18	10
values[5]	2893	1			T4	51		T6	20		T11	80
values[6]	3442	1			T4	43		T11	20		T12	4
values[7]	3004	1			T4	21		T11	27		T13	66

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24558

1

T4

402

T6

20

T9

12

auto[1]

413

1

T4

7

T11

6

T13

6

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	3	125	97.66	3

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[2] , values[3]]	[values[4]]	--	--	2
[auto[1]]	[values[7]]	[values[7]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	386	1			T11	26		T24	24		T30	27
auto[0]	values[0]	values[1]	211	1			T148	10		T149	24		T150	6
auto[0]	values[0]	values[2]	414	1			T13	25		T24	48		T28	19
auto[0]	values[0]	values[3]	310	1			T24	20		T31	18		T151	47
auto[0]	values[0]	values[4]	437	1			T11	40		T24	19		T76	10
auto[0]	values[0]	values[5]	246	1			T6	20		T23	20		T24	20
auto[0]	values[0]	values[6]	363	1			T4	20		T152	122		T153	35
auto[0]	values[0]	values[7]	200	1			T154	18		T114	4		T155	20
auto[0]	values[1]	values[0]	284	1			T11	20		T156	20		T157	16
auto[0]	values[1]	values[1]	323	1			T4	35		T13	31		T116	10
auto[0]	values[1]	values[2]	314	1			T26	34		T158	12		T30	46
auto[0]	values[1]	values[3]	273	1			T23	27		T26	20		T159	6
auto[0]	values[1]	values[4]	429	1			T11	20		T155	20		T122	20
auto[0]	values[1]	values[5]	330	1			T30	27		T160	16		T143	30
auto[0]	values[1]	values[6]	291	1			T12	4		T13	26		T161	8
auto[0]	values[1]	values[7]	308	1			T37	8		T144	40		T162	24
auto[0]	values[2]	values[0]	802	1			T13	28		T23	20		T24	123
auto[0]	values[2]	values[1]	340	1			T4	21		T163	8		T149	21
auto[0]	values[2]	values[2]	271	1			T11	22		T143	46		T151	38
auto[0]	values[2]	values[3]	548	1			T4	24		T164	4		T27	17
auto[0]	values[2]	values[4]	453	1			T18	10		T27	62		T143	20
auto[0]	values[2]	values[5]	335	1			T11	29		T165	45		T20	56
auto[0]	values[2]	values[6]	302	1			T23	20		T166	8		T167	4
auto[0]	values[2]	values[7]	602	1			T13	22		T23	26		T83	14
auto[0]	values[3]	values[0]	527	1			T168	22		T155	24		T169	70
auto[0]	values[3]	values[1]	334	1			T28	20		T170	18		T171	19
auto[0]	values[3]	values[2]	371	1			T135	12		T147	8		T143	20
auto[0]	values[3]	values[3]	531	1			T4	20		T24	31		T27	20
auto[0]	values[3]	values[4]	202	1			T13	20		T31	20		T172	18
auto[0]	values[3]	values[5]	299	1			T23	20		T31	62		T155	19
auto[0]	values[3]	values[6]	437	1			T38	8		T173	8		T155	20
auto[0]	values[3]	values[7]	461	1			T4	20		T11	27		T13	24
auto[0]	values[4]	values[0]	260	1			T24	20		T174	18		T122	24
auto[0]	values[4]	values[1]	524	1			T4	25		T175	6		T119	6
auto[0]	values[4]	values[2]	247	1			T17	10		T39	4		T176	69
auto[0]	values[4]	values[3]	441	1			T4	91		T27	20		T143	41
auto[0]	values[4]	values[4]	203	1			T13	23		T155	32		T177	65
auto[0]	values[4]	values[5]	550	1			T4	49		T23	20		T31	47
auto[0]	values[4]	values[6]	650	1			T27	41		T178	4		T31	49
auto[0]	values[4]	values[7]	408	1			T13	20		T23	20		T30	27
auto[0]	values[5]	values[0]	404	1			T13	41		T24	21		T31	25
auto[0]	values[5]	values[1]	322	1			T179	18		T162	20		T152	42
auto[0]	values[5]	values[2]	510	1			T13	24		T174	39		T144	20
auto[0]	values[5]	values[3]	365	1			T28	20		T177	40		T180	62
auto[0]	values[5]	values[4]	412	1			T99	2		T27	20		T181	6
auto[0]	values[5]	values[5]	239	1			T27	39		T28	20		T155	29
auto[0]	values[5]	values[6]	552	1			T24	20		T180	101		T182	20
auto[0]	values[5]	values[7]	448	1			T24	43		T27	19		T28	20
auto[0]	values[6]	values[0]	379	1			T115	2		T177	19		T122	40
auto[0]	values[6]	values[1]	267	1			T4	25		T23	19		T28	83
auto[0]	values[6]	values[2]	217	1			T27	23		T149	23		T155	21
auto[0]	values[6]	values[3]	580	1			T27	46		T30	20		T144	29
auto[0]	values[6]	values[4]	354	1			T23	20		T144	28		T183	24
auto[0]	values[6]	values[5]	308	1			T13	20		T113	20		T184	10
auto[0]	values[6]	values[6]	355	1			T27	29		T185	16		T171	19
auto[0]	values[6]	values[7]	370	1			T156	20		T186	36		T162	19
auto[0]	values[7]	values[0]	289	1			T4	27		T144	20		T177	20
auto[0]	values[7]	values[1]	641	1			T4	23		T9	12		T23	20
auto[0]	values[7]	values[2]	501	1			T24	49		T75	6		T156	162
auto[0]	values[7]	values[3]	203	1			T11	21		T28	21		T156	20
auto[0]	values[7]	values[4]	482	1			T13	21		T187	24		T28	40
auto[0]	values[7]	values[5]	542	1			T11	48		T27	43		T31	28
auto[0]	values[7]	values[6]	449	1			T4	22		T11	19		T188	2
auto[0]	values[7]	values[7]	152	1			T189	6		T190	40		T191	41
auto[1]	values[0]	values[0]	6	1			T11	2		T20	2		T128	2
auto[1]	values[0]	values[1]	7	1			T192	1		T193	6		-	-
auto[1]	values[0]	values[2]	5	1			T13	1		T28	1		T152	1
auto[1]	values[0]	values[3]	11	1			T31	2		T151	3		T152	1
auto[1]	values[0]	values[4]	10	1			T24	1		T29	2		T31	1
auto[1]	values[0]	values[5]	3	1			T194	2		T195	1		-	-
auto[1]	values[0]	values[6]	3	1			T196	1		T197	1		T198	1
auto[1]	values[0]	values[7]	4	1			T152	2		T124	2		-	-
auto[1]	values[1]	values[0]	3	1			T199	2		T200	1		-	-
auto[1]	values[1]	values[1]	4	1			T20	3		T201	1		-	-
auto[1]	values[1]	values[2]	8	1			T26	1		T30	1		T176	1
auto[1]	values[1]	values[3]	4	1			T123	2		T202	1		T197	1
auto[1]	values[1]	values[4]	4	1			T152	1		T203	1		T204	2
auto[1]	values[1]	values[5]	1	1			T152	1		-	-		-	-
auto[1]	values[1]	values[6]	7	1			T13	2		T205	4		T171	1
auto[1]	values[1]	values[7]	7	1			T162	1		T199	1		T153	3
auto[1]	values[2]	values[0]	13	1			T13	1		T24	2		T31	2
auto[1]	values[2]	values[1]	5	1			T149	2		T56	2		T191	1
auto[1]	values[2]	values[2]	3	1			T143	2		T206	1		-	-
auto[1]	values[2]	values[3]	12	1			T4	1		T27	3		T177	3
auto[1]	values[2]	values[5]	4	1			T11	1		T20	1		T207	1
auto[1]	values[2]	values[6]	2	1			T169	1		T208	1		-	-
auto[1]	values[2]	values[7]	17	1			T145	5		T146	1		T209	4
auto[1]	values[3]	values[0]	8	1			T169	2		T192	2		T210	1
auto[1]	values[3]	values[1]	5	1			T171	1		T122	1		T192	1
auto[1]	values[3]	values[2]	9	1			T149	1		T211	2		T20	2
auto[1]	values[3]	values[3]	9	1			T156	1		T149	3		T177	1
auto[1]	values[3]	values[5]	8	1			T31	1		T155	3		T212	2
auto[1]	values[3]	values[6]	8	1			T152	2		T213	2		T214	2
auto[1]	values[3]	values[7]	10	1			T4	1		T31	3		T124	3
auto[1]	values[4]	values[0]	6	1			T174	2		T122	1		T215	2
auto[1]	values[4]	values[1]	9	1			T180	4		T20	2		T124	3
auto[1]	values[4]	values[2]	9	1			T176	3		T169	1		T20	5
auto[1]	values[4]	values[3]	8	1			T4	2		T143	2		T216	2
auto[1]	values[4]	values[4]	3	1			T155	1		T177	1		T182	1
auto[1]	values[4]	values[5]	7	1			T4	2		T190	2		T193	1
auto[1]	values[4]	values[6]	8	1			T31	2		T155	1		T169	1
auto[1]	values[4]	values[7]	5	1			T30	3		T155	1		T123	1
auto[1]	values[5]	values[0]	9	1			T24	1		T31	2		T192	3
auto[1]	values[5]	values[1]	1	1			T217	1		-	-		-	-
auto[1]	values[5]	values[2]	7	1			T13	1		T174	3		T151	1
auto[1]	values[5]	values[3]	6	1			T177	3		T180	1		T203	1
auto[1]	values[5]	values[4]	5	1			T182	1		T199	2		T193	2
auto[1]	values[5]	values[5]	7	1			T27	3		T155	1		T198	3
auto[1]	values[5]	values[6]	2	1			T180	1		T195	1		-	-
auto[1]	values[5]	values[7]	8	1			T24	1		T27	1		T155	1
auto[1]	values[6]	values[0]	8	1			T177	2		T218	3		T204	2
auto[1]	values[6]	values[1]	6	1			T23	1		T28	1		T182	1
auto[1]	values[6]	values[2]	12	1			T27	1		T155	2		T182	3
auto[1]	values[6]	values[3]	15	1			T27	1		T144	3		T183	1
auto[1]	values[6]	values[4]	10	1			T183	2		T169	2		T219	2
auto[1]	values[6]	values[5]	8	1			T122	1		T191	3		T193	1
auto[1]	values[6]	values[6]	6	1			T171	1		T177	2		T220	1
auto[1]	values[6]	values[7]	4	1			T162	1		T219	1		T199	1
auto[1]	values[7]	values[0]	4	1			T145	1		T221	2		T197	1
auto[1]	values[7]	values[1]	10	1			T155	2		T145	3		T222	4
auto[1]	values[7]	values[2]	10	1			T156	1		T183	1		T171	1
auto[1]	values[7]	values[3]	1	1			T207	1		-	-		-	-
auto[1]	values[7]	values[4]	6	1			T13	1		T124	1		T223	2
auto[1]	values[7]	values[5]	6	1			T11	2		T27	1		T31	1
auto[1]	values[7]	values[6]	7	1			T4	1		T11	1		T143	1