Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1888

1

T1

13

T4

10

T5

3

auto[1]

1833

1

T1

12

T4

7

T5

2

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1981

1

T4

17

T11

8

T13

3

auto[1]

1740

1

T1

25

T5

5

T11

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2956

1

T1

25

T4

12

T5

5

auto[1]

765

1

T4

5

T11

4

T13

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	762	1			T1	10		T4	6		T5	2
valid[1]	773	1			T1	3		T4	4		T5	1
valid[2]	733	1			T4	3		T5	1		T11	3
valid[3]	730	1			T1	6		T4	3		T13	2
valid[4]	723	1			T1	6		T4	1		T5	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	125	1			T4	3		T11	1		T13	1
auto[0]	auto[0]	valid[0]	auto[1]	186	1			T1	5		T5	2		T11	1
auto[0]	auto[0]	valid[1]	auto[0]	124	1			T4	2		T22	7		T68	2
auto[0]	auto[0]	valid[1]	auto[1]	189	1			T1	2		T5	1		T15	1
auto[0]	auto[0]	valid[2]	auto[0]	119	1			T4	1		T11	1		T14	2
auto[0]	auto[0]	valid[2]	auto[1]	192	1			T11	1		T13	1		T23	1
auto[0]	auto[0]	valid[3]	auto[0]	131	1			T4	2		T14	3		T22	1
auto[0]	auto[0]	valid[3]	auto[1]	164	1			T1	2		T293	4		T294	1
auto[0]	auto[0]	valid[4]	auto[0]	113	1			T4	1		T14	1		T22	1
auto[0]	auto[0]	valid[4]	auto[1]	165	1			T1	4		T11	1		T13	3
auto[0]	auto[1]	valid[0]	auto[0]	119	1			T4	2		T14	2		T15	1
auto[0]	auto[1]	valid[0]	auto[1]	179	1			T1	5		T66	2		T67	1
auto[0]	auto[1]	valid[1]	auto[0]	121	1			T14	4		T22	2		T28	1
auto[0]	auto[1]	valid[1]	auto[1]	171	1			T1	1		T16	1		T293	1
auto[0]	auto[1]	valid[2]	auto[0]	118	1			T4	1		T11	1		T15	1
auto[0]	auto[1]	valid[2]	auto[1]	160	1			T5	1		T66	1		T67	1
auto[0]	auto[1]	valid[3]	auto[0]	127	1			T13	1		T14	1		T22	5
auto[0]	auto[1]	valid[3]	auto[1]	151	1			T1	4		T66	2		T67	2
auto[0]	auto[1]	valid[4]	auto[0]	119	1			T11	1		T14	2		T22	1
auto[0]	auto[1]	valid[4]	auto[1]	183	1			T1	2		T5	1		T13	1
auto[1]	auto[0]	valid[0]	auto[0]	72	1			T11	1		T14	1		T15	1
auto[1]	auto[0]	valid[1]	auto[0]	87	1			T11	2		T14	1		T16	1
auto[1]	auto[0]	valid[2]	auto[0]	73	1			T14	2		T22	1		T23	1
auto[1]	auto[0]	valid[3]	auto[0]	78	1			T4	1		T14	3		T15	3
auto[1]	auto[0]	valid[4]	auto[0]	70	1			T14	2		T68	1		T65	1
auto[1]	auto[1]	valid[0]	auto[0]	81	1			T4	1		T14	1		T15	1
auto[1]	auto[1]	valid[1]	auto[0]	81	1			T4	2		T14	1		T23	1
auto[1]	auto[1]	valid[2]	auto[0]	71	1			T4	1		T14	2		T24	1
auto[1]	auto[1]	valid[3]	auto[0]	79	1			T13	1		T68	1		T30	1
auto[1]	auto[1]	valid[4]	auto[0]	73	1			T11	1		T14	1		T22	3

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal