Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	765	1			T4	14		T22	4		T28	11
all_values[1]	765	1			T4	14		T22	4		T28	11
all_values[2]	765	1			T4	14		T22	4		T28	11
all_values[3]	765	1			T4	14		T22	4		T28	11
all_values[4]	765	1			T4	14		T22	4		T28	11
all_values[5]	765	1			T4	14		T22	4		T28	11
all_values[6]	765	1			T4	14		T22	4		T28	11
all_values[7]	765	1			T4	14		T22	4		T28	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3184

1

T4

68

T22

20

T28

42

auto[1]

2936

1

T4

44

T22

12

T28

46

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2381

1

T4

35

T22

15

T28

45

auto[1]

3739

1

T4

77

T22

17

T28

43

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3455

1

T4

56

T22

18

T28

63

auto[1]

2665

1

T4

56

T22

14

T28

25

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	162	1			T4	4		T22	2		T28	5
all_values[0]	auto[0]	auto[0]	auto[1]	78	1			T141	2		T142	1		T144	4
all_values[0]	auto[0]	auto[1]	auto[0]	117	1			T22	2		T28	4		T46	1
all_values[0]	auto[0]	auto[1]	auto[1]	88	1			T4	5		T46	1		T141	7
all_values[0]	auto[1]	auto[0]	auto[1]	160	1			T4	4		T28	1		T46	2
all_values[0]	auto[1]	auto[1]	auto[1]	160	1			T4	1		T28	1		T46	7
all_values[1]	auto[0]	auto[0]	auto[0]	136	1			T4	3		T22	1		T28	4
all_values[1]	auto[0]	auto[0]	auto[1]	96	1			T4	2		T22	1		T28	2
all_values[1]	auto[0]	auto[1]	auto[0]	119	1			T28	2		T46	3		T30	1
all_values[1]	auto[0]	auto[1]	auto[1]	73	1			T4	2		T30	1		T141	3
all_values[1]	auto[1]	auto[0]	auto[1]	183	1			T4	3		T22	2		T28	2
all_values[1]	auto[1]	auto[1]	auto[1]	158	1			T4	4		T28	1		T46	4
all_values[2]	auto[0]	auto[0]	auto[0]	134	1			T4	3		T28	4		T46	3
all_values[2]	auto[0]	auto[0]	auto[1]	64	1			T4	1		T46	1		T141	3
all_values[2]	auto[0]	auto[1]	auto[0]	139	1			T22	2		T28	4		T46	7
all_values[2]	auto[0]	auto[1]	auto[1]	79	1			T4	1		T28	1		T141	3
all_values[2]	auto[1]	auto[0]	auto[1]	178	1			T4	5		T22	1		T46	2
all_values[2]	auto[1]	auto[1]	auto[1]	171	1			T4	4		T22	1		T28	2
all_values[3]	auto[0]	auto[0]	auto[0]	129	1			T4	6		T46	1		T30	1
all_values[3]	auto[0]	auto[0]	auto[1]	73	1			T4	1		T22	1		T46	1
all_values[3]	auto[0]	auto[1]	auto[0]	142	1			T4	3		T28	1		T46	3
all_values[3]	auto[0]	auto[1]	auto[1]	87	1			T28	4		T46	2		T141	1
all_values[3]	auto[1]	auto[0]	auto[1]	170	1			T4	2		T22	3		T30	1
all_values[3]	auto[1]	auto[1]	auto[1]	164	1			T4	2		T28	6		T46	7
all_values[4]	auto[0]	auto[0]	auto[0]	151	1			T4	1		T22	1		T28	2
all_values[4]	auto[0]	auto[0]	auto[1]	76	1			T4	2		T28	2		T46	2
all_values[4]	auto[0]	auto[1]	auto[0]	133	1			T4	2		T22	1		T28	2
all_values[4]	auto[0]	auto[1]	auto[1]	73	1			T4	2		T22	1		T28	3
all_values[4]	auto[1]	auto[0]	auto[1]	170	1			T4	5		T28	2		T46	4
all_values[4]	auto[1]	auto[1]	auto[1]	162	1			T4	2		T22	1		T46	4
all_values[5]	auto[0]	auto[0]	auto[0]	224	1			T4	4		T28	4		T46	3
all_values[5]	auto[0]	auto[1]	auto[0]	214	1			T4	3		T22	3		T28	4
all_values[5]	auto[1]	auto[0]	auto[1]	174	1			T4	4		T22	1		T28	2
all_values[5]	auto[1]	auto[1]	auto[1]	153	1			T4	3		T28	1		T46	3
all_values[6]	auto[0]	auto[0]	auto[0]	163	1			T4	2		T22	1		T28	3
all_values[6]	auto[0]	auto[0]	auto[1]	69	1			T4	2		T28	2		T46	3
all_values[6]	auto[0]	auto[1]	auto[0]	142	1			T4	1		T28	1		T46	2
all_values[6]	auto[0]	auto[1]	auto[1]	73	1			T4	1		T28	2		T46	1
all_values[6]	auto[1]	auto[0]	auto[1]	171	1			T4	6		T22	3		T28	1
all_values[6]	auto[1]	auto[1]	auto[1]	147	1			T4	2		T28	2		T46	3
all_values[7]	auto[0]	auto[0]	auto[0]	166	1			T4	1		T22	2		T28	5
all_values[7]	auto[0]	auto[0]	auto[1]	73	1			T28	1		T46	1		T141	1
all_values[7]	auto[0]	auto[1]	auto[0]	110	1			T4	2		T46	3		T30	1
all_values[7]	auto[0]	auto[1]	auto[1]	72	1			T4	2		T28	1		T46	3
all_values[7]	auto[1]	auto[0]	auto[1]	184	1			T4	7		T22	1		T46	4
all_values[7]	auto[1]	auto[1]	auto[1]	160	1			T4	2		T22	1		T28	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal