Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49794

1

T3

5

T4

271

T11

118

auto[1]

18256

1

T1

319

T5

5

T11

30

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49776

1

T1

319

T3

4

T4

178

auto[1]

18274

1

T3

1

T4

93

T11

47

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35195	1			T1	165		T3	2		T4	143
others[1]	5660	1			T1	26		T3	1		T4	21
others[2]	5674	1			T1	22		T4	26		T11	16
others[3]	6320	1			T1	28		T3	1		T4	24
interest[1]	3761	1			T1	24		T4	13		T11	9
interest[4]	23128	1			T1	102		T4	93		T5	5
interest[64]	11440	1			T1	54		T3	1		T4	44

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16231	1			T3	1		T4	95		T11	37
auto[0]	auto[0]	others[1]	2604	1			T3	1		T4	14		T11	8
auto[0]	auto[0]	others[2]	2676	1			T4	16		T11	5		T13	10
auto[0]	auto[0]	others[3]	2897	1			T3	1		T4	14		T11	9
auto[0]	auto[0]	interest[1]	1727	1			T4	8		T11	3		T13	2
auto[0]	auto[0]	interest[4]	10646	1			T4	60		T11	23		T13	27
auto[0]	auto[0]	interest[64]	5385	1			T3	1		T4	31		T11	9
auto[0]	auto[1]	others[0]	9567	1			T1	165		T5	5		T11	17
auto[0]	auto[1]	others[1]	1514	1			T1	26		T11	2		T13	6
auto[0]	auto[1]	others[2]	1472	1			T1	22		T11	3		T13	3
auto[0]	auto[1]	others[3]	1741	1			T1	28		T11	3		T13	10
auto[0]	auto[1]	interest[1]	1045	1			T1	24		T11	1		T13	2
auto[0]	auto[1]	interest[4]	6354	1			T1	102		T5	5		T11	7
auto[0]	auto[1]	interest[64]	2917	1			T1	54		T11	4		T13	16
auto[1]	auto[0]	others[0]	9397	1			T3	1		T4	48		T11	23
auto[1]	auto[0]	others[1]	1542	1			T4	7		T11	2		T13	4
auto[1]	auto[0]	others[2]	1526	1			T4	10		T11	8		T13	6
auto[1]	auto[0]	others[3]	1682	1			T4	10		T11	3		T13	8
auto[1]	auto[0]	interest[1]	989	1			T4	5		T11	5		T13	2
auto[1]	auto[0]	interest[4]	6128	1			T4	33		T11	15		T13	42
auto[1]	auto[0]	interest[64]	3138	1			T4	13		T11	6		T13	15

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal