Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2218972	1			T1	15057		T2	1		T4	10429
all_values[1]	2218972	1			T1	15057		T2	1		T4	10429
all_values[2]	2218972	1			T1	15057		T2	1		T4	10429
all_values[3]	2218972	1			T1	15057		T2	1		T4	10429
all_values[4]	2218972	1			T1	15057		T2	1		T4	10429
all_values[5]	2218972	1			T1	15057		T2	1		T4	10429
all_values[6]	2218972	1			T1	15057		T2	1		T4	10429
all_values[7]	2218972	1			T1	15057		T2	1		T4	10429

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16942475

1

T1

120428

T2

8

T4

83432

auto[1]

809301

1

T1

28

T16

67

T27

91397

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17732342

1

T1

120359

T2

8

T4

83432

auto[1]

19434

1

T1

97

T6

2

T16

391

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2083006	1			T1	14994		T2	1		T4	10429
all_values[0]	auto[0]	auto[1]	10029	1			T1	62		T16	243		T27	92
all_values[0]	auto[1]	auto[0]	125494	1			T1	1		T16	6		T27	18227
all_values[0]	auto[1]	auto[1]	443	1			T16	6		T27	51		T30	3
all_values[1]	auto[0]	auto[0]	2093078	1			T1	15036		T2	1		T4	10429
all_values[1]	auto[0]	auto[1]	4689	1			T1	15		T16	67		T27	1
all_values[1]	auto[1]	auto[0]	120912	1			T1	4		T16	7		T27	18273
all_values[1]	auto[1]	auto[1]	293	1			T1	2		T16	4		T27	4
all_values[2]	auto[0]	auto[0]	2216496	1			T1	15048		T2	1		T4	10429
all_values[2]	auto[0]	auto[1]	1725	1			T1	8		T16	28		T27	2
all_values[2]	auto[1]	auto[0]	553	1			T1	1		T16	4		T27	2
all_values[2]	auto[1]	auto[1]	198	1			T16	4		T27	1		T30	3
all_values[3]	auto[0]	auto[0]	2089320	1			T1	15055		T2	1		T4	10429
all_values[3]	auto[0]	auto[1]	182	1			T16	5		T27	2		T30	4
all_values[3]	auto[1]	auto[0]	129292	1			T16	1		T27	18273		T30	2
all_values[3]	auto[1]	auto[1]	178	1			T1	2		T16	7		T27	3
all_values[4]	auto[0]	auto[0]	2123021	1			T1	15055		T2	1		T4	10429
all_values[4]	auto[0]	auto[1]	197	1			T1	2		T16	2		T27	2
all_values[4]	auto[1]	auto[0]	95564	1			T16	3		T27	3		T30	4
all_values[4]	auto[1]	auto[1]	190	1			T16	5		T27	1		T30	4
all_values[5]	auto[0]	auto[0]	2168281	1			T1	15051		T2	1		T4	10429
all_values[5]	auto[0]	auto[1]	327	1			T6	2		T16	1		T27	3
all_values[5]	auto[1]	auto[0]	50152	1			T1	4		T16	4		T27	3
all_values[5]	auto[1]	auto[1]	212	1			T1	2		T16	3		T27	1
all_values[6]	auto[0]	auto[0]	2096020	1			T1	15051		T2	1		T4	10429
all_values[6]	auto[0]	auto[1]	190	1			T16	7		T27	1		T30	2
all_values[6]	auto[1]	auto[0]	122559	1			T1	3		T16	4		T27	18274
all_values[6]	auto[1]	auto[1]	203	1			T1	3		T16	3		T27	2
all_values[7]	auto[0]	auto[0]	2055733	1			T1	15050		T2	1		T4	10429
all_values[7]	auto[0]	auto[1]	181	1			T1	1		T16	3		T55	1
all_values[7]	auto[1]	auto[0]	162861	1			T1	6		T16	3		T27	18275
all_values[7]	auto[1]	auto[1]	197	1			T16	3		T27	4		T69	2