Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	28742	1			T1	76		T2	6		T5	10
auto[SpiFlashAddrCfg]	6308	1			T1	23		T2	6		T7	31
auto[SpiFlashAddr3b]	7488	1			T1	27		T2	4		T7	29
auto[SpiFlashAddr4b]	6135	1			T1	31		T2	2		T7	34

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27544

1

T1

87

T2

18

T5

10

auto[1]

21129

1

T1

70

T7

98

T16

377

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26459

1

T1

93

T2

6

T5

10

auto[1]

22214

1

T1

64

T2

12

T7

101

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	32745	1			T1	91		T2	8		T5	10
values[1]	901	1			T1	4		T7	6		T16	15
values[2]	1215	1			T1	3		T7	4		T16	12
values[3]	1134	1			T1	8		T7	3		T16	15
values[4]	1145	1			T1	1		T7	8		T16	21
values[5]	1202	1			T1	5		T7	8		T11	1
values[6]	1159	1			T1	1		T7	10		T16	16
values[7]	1290	1			T1	9		T7	4		T16	18
values[8]	7882	1			T1	35		T2	10		T7	26

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24705

1

T1

157

T2

18

T5

10

auto[1]

23968

1

T7

200

T11

2

T14

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

46937

1

T1

146

T2

18

T5

10

write

1736

1

T1

11

T7

3

T16

25

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

15988

1

T1

70

T2

8

T5

10

valids[0x1]

32685

1

T1

87

T2

10

T7

119

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1302	1			T1	3		T2	4		T7	7
internal_process_ops[0x5a]	1386	1			T1	4		T7	6		T12	2
internal_process_ops[0x05]	17454	1			T1	18		T2	2		T7	44
internal_process_ops[0x35]	1206	1			T1	6		T7	4		T16	22
internal_process_ops[0x15]	1325	1			T1	4		T7	8		T16	31
internal_process_ops[0x03]	880	1			T1	5		T7	2		T14	1
internal_process_ops[0x0b]	842	1			T1	8		T7	2		T16	9
internal_process_ops[0x3b]	805	1			T1	3		T2	4		T7	2
internal_process_ops[0x6b]	882	1			T1	3		T7	1		T14	1
internal_process_ops[0xbb]	848	1			T1	5		T7	4		T11	1
internal_process_ops[0xeb]	831	1			T1	4		T7	1		T14	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47855

1

T1

150

T2

18

T5

10

auto[1]

818

1

T1

7

T16

15

T25

3

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47050

1

T1

152

T2

18

T5

10

auto[1]

1623

1

T1

5

T7

8

T16

23

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8837

1

T1

49

T2

6

T5

10

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

4544

1

T1

21

T16

35

T167

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1740

1

T1

10

T2

6

T16

28

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1516

1

T1

13

T16

17

T29

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2094

1

T1

11

T2

4

T16

31

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1858

1

T1

12

T16

26

T29

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1774

1

T1

12

T2

2

T12

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1509

1

T1

18

T16

30

T167

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

59

1

T168

2

T30

7

T169

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

60

1

T1

1

T16

1

T27

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

34

1

T1

2

T27

2

T30

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

45

1

T1

3

T31

2

T69

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

89

1

T27

3

T30

1

T33

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

45

1

T30

2

T33

1

T170

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

51

1

T28

1

T30

1

T69

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

60

1

T27

3

T28

4

T81

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

57

1

T1

1

T16

1

T31

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

50

1

T1

2

T31

2

T35

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

39

1

T1

1

T16

1

T27

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

45

1

T16

1

T30

1

T34

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

68

1

T22

2

T171

4

T71

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

43

1

T1

1

T27

1

T30

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

39

1

T172

2

T71

4

T173

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

49

1

T16

3

T69

1

T35

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

7957

1

T7

50

T16

158

T25

70

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6960

1

T7

55

T16

190

T25

61

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1322

1

T7

22

T11

1

T14

1

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1259

1

T7

9

T16

19

T25

16

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1624

1

T7

13

T11

1

T14

2

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1524

1

T7

15

T16

27

T25

27

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1227

1

T7

15

T16

17

T25

17

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1192

1

T7

18

T16

21

T25

23

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

68

1

T16

1

T55

1

T70

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

60

1

T16

2

T25

1

T55

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

56

1

T7

1

T70

1

T174

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

62

1

T16

1

T39

1

T175

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

58

1

T16

1

T176

1

T177

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

61

1

T16

5

T25

1

T176

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

57

1

T16

2

T69

1

T177

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

50

1

T16

1

T69

2

T128

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

61

1

T7

1

T25

1

T55

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

54

1

T176

1

T174

1

T162

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

39

1

T16

2

T128

1

T162

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

43

1

T25

1

T69

6

T177

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

81

1

T7

1

T16

1

T25

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

55

1

T16

1

T176

4

T177

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

62

1

T16

1

T25

2

T176

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

36

1

T176

1

T177

1

T70

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3354	1			T1	34		T5	10		T16	49
auto[0]	values[0]	valids[0x1]	12356	1			T1	57		T2	8		T16	80
auto[0]	values[1]	valids[0x1]	450	1			T1	4		T16	2		T32	4
auto[0]	values[2]	valids[0x0]	472	1			T16	2		T27	6		T28	1
auto[0]	values[2]	valids[0x1]	260	1			T1	3		T16	4		T27	2
auto[0]	values[3]	valids[0x0]	390	1			T1	3		T16	2		T27	8
auto[0]	values[3]	valids[0x1]	202	1			T1	5		T16	4		T27	3
auto[0]	values[4]	valids[0x0]	447	1			T1	1		T16	8		T32	4
auto[0]	values[4]	valids[0x1]	222	1			T16	5		T27	8		T178	1
auto[0]	values[5]	valids[0x0]	446	1			T1	2		T15	2		T16	4
auto[0]	values[5]	valids[0x1]	239	1			T1	3		T12	2		T16	1
auto[0]	values[6]	valids[0x0]	423	1			T16	6		T27	3		T28	2
auto[0]	values[6]	valids[0x1]	242	1			T1	1		T16	1		T27	1
auto[0]	values[7]	valids[0x0]	461	1			T1	3		T16	8		T32	6
auto[0]	values[7]	valids[0x1]	291	1			T1	6		T16	8		T179	2
auto[0]	values[8]	valids[0x0]	2722	1			T1	27		T2	8		T12	4
auto[0]	values[8]	valids[0x1]	1728	1			T1	8		T2	2		T16	29
auto[1]	values[0]	valids[0x0]	3424	1			T7	47		T16	63		T25	34
auto[1]	values[0]	valids[0x1]	13611	1			T7	84		T14	1		T16	318
auto[1]	values[1]	valids[0x1]	451	1			T7	6		T16	13		T25	4
auto[1]	values[2]	valids[0x0]	281	1			T7	3		T16	2		T25	10
auto[1]	values[2]	valids[0x1]	202	1			T7	1		T16	4		T25	2
auto[1]	values[3]	valids[0x0]	329	1			T7	3		T16	2		T25	6
auto[1]	values[3]	valids[0x1]	213	1			T16	7		T25	5		T55	1
auto[1]	values[4]	valids[0x0]	267	1			T7	2		T16	4		T25	5
auto[1]	values[4]	valids[0x1]	209	1			T7	6		T16	4		T25	1
auto[1]	values[5]	valids[0x0]	278	1			T7	3		T11	1		T16	5
auto[1]	values[5]	valids[0x1]	239	1			T7	5		T16	9		T55	2
auto[1]	values[6]	valids[0x0]	290	1			T7	7		T16	4		T25	9
auto[1]	values[6]	valids[0x1]	204	1			T7	3		T16	5		T25	3
auto[1]	values[7]	valids[0x0]	330	1			T7	2		T25	1		T39	2
auto[1]	values[7]	valids[0x1]	208	1			T7	2		T16	2		T25	5
auto[1]	values[8]	valids[0x0]	2074	1			T7	14		T11	1		T14	2
auto[1]	values[8]	valids[0x1]	1358	1			T7	12		T16	22		T25	20