Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2844115

1

T1

9428

T2

1

T5

47

auto[1]

16136

1

T1

17

T7

40

T16

237

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

954466

1

T1

38

T2

1

T5

47

auto[1]

1905785

1

T1

9407

T7

4636

T16

38154

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	530785	1			T1	270		T2	1		T7	1486
auto[524288:1048575]	355470	1			T1	5676		T7	515		T12	782
auto[1048576:1572863]	343599	1			T5	39		T7	431		T11	30
auto[1572864:2097151]	315955	1			T1	4		T7	268		T10	2
auto[2097152:2621439]	329196	1			T1	393		T7	1330		T11	17
auto[2621440:3145727]	296401	1			T1	128		T5	3		T7	631
auto[3145728:3670015]	351707	1			T1	2710		T7	7		T12	40
auto[3670016:4194303]	337138	1			T1	264		T5	5		T7	23

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1924098

1

T1

9445

T2

1

T5

47

auto[1]

936153

1

T7

7

T10

211

T11

243

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2471673

1

T1

3759

T2

1

T5

39

auto[1]

388578

1

T1

5686

T5

8

T7

1044

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	227357	1			T1	6		T2	1		T7	9
auto[0]	auto[0]	auto[0:524287]	auto[1]	263087	1			T1	259		T7	1468		T16	3607
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	131226	1			T1	1		T7	1		T12	782
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	177985	1			T7	512		T16	6654		T25	1569
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	103011	1			T5	39		T7	2		T11	30
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	165966	1			T7	429		T16	4802		T25	256
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	67269	1			T1	1		T7	7		T10	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	191189	1			T7	258		T16	2124		T25	261
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	74949	1			T1	6		T7	6		T11	17
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	208438	1			T1	386		T7	536		T16	1559
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	107243	1			T7	5		T12	780		T16	20
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	151367	1			T1	128		T7	370		T16	4636
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	95555	1			T7	3		T12	40		T14	2652
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	201498	1			T1	2704		T7	4		T16	6416
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	135453	1			T1	7		T7	5		T10	116
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	157254	1			T1	256		T7	2		T16	341
auto[0]	auto[1]	auto[0:524287]	auto[0]	454	1			T1	1		T16	4		T27	4
auto[0]	auto[1]	auto[0:524287]	auto[1]	37503	1			T16	3385		T27	513		T33	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1343	1			T1	6		T7	2		T16	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	43045	1			T1	5657		T31	256		T69	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	3086	1			T16	2		T28	2		T30	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	68754	1			T16	2		T28	1		T30	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	2170	1			T1	3		T16	5		T27	3
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	53657	1			T16	2		T27	3009		T69	2104
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	254	1			T7	6		T16	6		T27	5
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	43734	1			T7	769		T16	2283		T30	512
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	2315	1			T5	3		T16	5		T27	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	33623	1			T7	256		T16	725		T27	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	214	1			T1	1		T16	3		T27	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	52175	1			T1	5		T16	1		T27	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	943	1			T1	1		T5	5		T7	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	41998	1			T16	1403		T25	822		T28	258
auto[1]	auto[0]	auto[0:524287]	auto[0]	219	1			T1	2		T7	2		T25	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	1872	1			T1	2		T7	7		T25	4
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	152	1			T16	3		T30	3		T31	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1494	1			T16	5		T30	5		T31	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	164	1			T16	1		T28	2		T31	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2015	1			T16	36		T28	31		T31	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	164	1			T7	2		T16	4		T30	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1194	1			T7	1		T16	47		T30	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	134	1			T1	1		T7	1		T16	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1285	1			T7	2		T16	63		T25	22
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	165	1			T16	4		T25	1		T27	5
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1348	1			T16	12		T25	12		T27	20
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	153	1			T16	1		T25	2		T27	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1423	1			T25	12		T27	14		T30	4
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	154	1			T7	2		T16	1		T25	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	890	1			T7	13		T16	7		T25	1
auto[1]	auto[1]	auto[0:524287]	auto[0]	36	1			T27	1		T33	1		T22	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	257	1			T27	1		T33	18		T220	3
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	23	1			T1	2		T69	1		T220	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	202	1			T1	10		T69	9		T220	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	61	1			T16	2		T28	1		T30	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	542	1			T16	10		T28	13		T30	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	36	1			T16	2		T69	3		T186	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	276	1			T16	2		T69	13		T186	4
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	41	1			T7	1		T16	1		T176	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	361	1			T7	9		T16	20		T176	5
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	42	1			T27	1		T174	2		T192	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	298	1			T174	12		T192	7		T71	16
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	43	1			T16	1		T27	1		T70	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	646	1			T16	12		T27	21		T70	78
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	37	1			T16	1		T25	1		T28	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	409	1			T25	13		T28	13		T176	20

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1531665	1			T1	3754		T2	1		T5	39
auto[0]	auto[0]	auto[1]	927182	1			T7	2		T10	211		T11	243
auto[0]	auto[1]	auto[0]	376586	1			T1	5674		T5	8		T7	1033
auto[0]	auto[1]	auto[1]	8682	1			T7	1		T25	1		T27	1
auto[1]	auto[0]	auto[0]	12584	1			T1	5		T7	27		T16	183
auto[1]	auto[0]	auto[1]	242	1			T7	3		T16	3		T25	6
auto[1]	auto[1]	auto[0]	3263	1			T1	12		T7	9		T16	50
auto[1]	auto[1]	auto[1]	47	1			T7	1		T16	1		T25	1