Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14916

1

T1

87

T2

18

T5

10

auto[1]

9789

1

T1

70

T16

113

T29

4

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3562	1			T1	21		T16	20		T27	58
values[1]	3076	1			T1	44		T16	66		T27	41
values[2]	3123	1			T1	20		T16	20		T29	4
values[3]	3525	1			T1	20		T5	10		T16	20
values[4]	3230	1			T16	40		T27	40		T28	67
values[5]	2800	1			T2	18		T15	2		T16	42
values[6]	2963	1			T1	32		T16	27		T63	2
values[7]	2426	1			T1	20		T12	6		T16	26

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3316	1			T1	20		T16	25		T29	4
values[1]	3638	1			T15	2		T16	46		T30	20
values[2]	3083	1			T1	40		T180	6		T27	20
values[3]	2883	1			T1	32		T16	20		T167	14
values[4]	2986	1			T1	21		T12	6		T16	61
values[5]	2910	1			T5	10		T16	27		T32	20
values[6]	2767	1			T1	44		T2	18		T16	62
values[7]	3122	1			T16	20		T63	2		T68	8

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	207	1			T28	58		T36	10		T304	2
auto[0]	values[0]	values[1]	201	1			T69	13		T305	12		T215	12
auto[0]	values[0]	values[2]	355	1			T35	22		T84	16		T36	9
auto[0]	values[0]	values[3]	177	1			T27	14		T69	27		T160	11
auto[0]	values[0]	values[4]	242	1			T1	12		T186	7		T198	5
auto[0]	values[0]	values[5]	229	1			T30	11		T69	13		T173	11
auto[0]	values[0]	values[6]	214	1			T306	8		T160	24		T224	47
auto[0]	values[0]	values[7]	368	1			T16	14		T33	12		T192	10
auto[0]	values[1]	values[0]	199	1			T16	14		T30	14		T36	9
auto[0]	values[1]	values[1]	235	1			T33	11		T81	10		T160	13
auto[0]	values[1]	values[2]	222	1			T307	2		T213	17		T308	10
auto[0]	values[1]	values[3]	224	1			T27	14		T227	8		T153	29
auto[0]	values[1]	values[4]	261	1			T16	9		T31	8		T216	10
auto[0]	values[1]	values[5]	236	1			T95	6		T30	28		T69	8
auto[0]	values[1]	values[6]	150	1			T1	18		T16	11		T27	9
auto[0]	values[1]	values[7]	193	1			T96	4		T30	14		T22	31
auto[0]	values[2]	values[0]	322	1			T28	45		T69	9		T221	18
auto[0]	values[2]	values[1]	296	1			T30	11		T183	13		T309	10
auto[0]	values[2]	values[2]	334	1			T1	10		T30	10		T22	10
auto[0]	values[2]	values[3]	205	1			T22	10		T191	2		T184	8
auto[0]	values[2]	values[4]	165	1			T31	15		T194	18		T263	15
auto[0]	values[2]	values[5]	112	1			T27	7		T310	4		T198	8
auto[0]	values[2]	values[6]	160	1			T16	10		T31	12		T183	15
auto[0]	values[2]	values[7]	327	1			T219	6		T183	25		T207	6
auto[0]	values[3]	values[0]	178	1			T1	12		T200	12		T158	8
auto[0]	values[3]	values[1]	282	1			T178	29		T22	13		T231	6
auto[0]	values[3]	values[2]	405	1			T180	6		T27	17		T311	12
auto[0]	values[3]	values[3]	195	1			T198	11		T188	4		T47	12
auto[0]	values[3]	values[4]	366	1			T16	12		T88	8		T81	12
auto[0]	values[3]	values[5]	261	1			T5	10		T27	6		T42	27
auto[0]	values[3]	values[6]	189	1			T27	11		T222	4		T36	9
auto[0]	values[3]	values[7]	328	1			T168	18		T172	11		T225	22
auto[0]	values[4]	values[0]	200	1			T35	6		T223	10		T295	10
auto[0]	values[4]	values[1]	367	1			T16	11		T198	57		T266	13
auto[0]	values[4]	values[2]	221	1			T30	8		T202	9		T183	11
auto[0]	values[4]	values[3]	178	1			T16	10		T27	12		T28	10
auto[0]	values[4]	values[4]	183	1			T227	9		T173	11		T244	10
auto[0]	values[4]	values[5]	191	1			T36	8		T160	14		T283	10
auto[0]	values[4]	values[6]	210	1			T28	12		T183	9		T312	10
auto[0]	values[4]	values[7]	308	1			T27	9		T220	11		T190	33
auto[0]	values[5]	values[0]	278	1			T30	14		T69	12		T35	12
auto[0]	values[5]	values[1]	196	1			T15	2		T31	18		T313	9
auto[0]	values[5]	values[2]	111	1			T314	6		T153	19		T315	4
auto[0]	values[5]	values[3]	181	1			T181	6		T35	8		T316	16
auto[0]	values[5]	values[4]	153	1			T16	7		T214	10		T205	20
auto[0]	values[5]	values[5]	382	1			T69	38		T71	42		T129	110
auto[0]	values[5]	values[6]	183	1			T2	18		T16	19		T69	17
auto[0]	values[5]	values[7]	171	1			T27	13		T300	10		T172	8
auto[0]	values[6]	values[0]	385	1			T27	31		T35	14		T36	14
auto[0]	values[6]	values[1]	220	1			T35	16		T171	65		T71	13
auto[0]	values[6]	values[2]	196	1			T30	8		T33	33		T183	6
auto[0]	values[6]	values[3]	246	1			T1	23		T81	14		T185	8
auto[0]	values[6]	values[4]	283	1			T30	16		T71	13		T317	2
auto[0]	values[6]	values[5]	297	1			T16	12		T179	10		T318	20
auto[0]	values[6]	values[6]	208	1			T186	16		T266	15		T129	7
auto[0]	values[6]	values[7]	159	1			T63	2		T68	8		T172	15
auto[0]	values[7]	values[0]	187	1			T30	12		T178	16		T217	16
auto[0]	values[7]	values[1]	266	1			T16	19		T31	8		T97	4
auto[0]	values[7]	values[2]	132	1			T1	12		T319	6		T320	6
auto[0]	values[7]	values[3]	216	1			T211	10		T81	14		T35	32
auto[0]	values[7]	values[4]	105	1			T12	6		T202	9		T183	12
auto[0]	values[7]	values[5]	176	1			T32	20		T82	6		T31	15
auto[0]	values[7]	values[6]	241	1			T169	4		T170	14		T230	12
auto[0]	values[7]	values[7]	248	1			T27	45		T31	16		T69	15
auto[1]	values[0]	values[0]	296	1			T28	11		T36	10		T153	6
auto[1]	values[0]	values[1]	310	1			T69	7		T215	22		T321	2
auto[1]	values[0]	values[2]	169	1			T35	7		T36	65		T170	9
auto[1]	values[0]	values[3]	205	1			T27	44		T69	13		T160	9
auto[1]	values[0]	values[4]	168	1			T1	9		T186	13		T198	15
auto[1]	values[0]	values[5]	150	1			T30	10		T69	7		T173	9
auto[1]	values[0]	values[6]	154	1			T160	6		T266	7		T267	8
auto[1]	values[0]	values[7]	117	1			T16	6		T33	8		T192	10
auto[1]	values[1]	values[0]	221	1			T16	11		T30	8		T36	11
auto[1]	values[1]	values[1]	162	1			T33	9		T81	15		T160	7
auto[1]	values[1]	values[2]	64	1			T213	3		T234	7		T73	9
auto[1]	values[1]	values[3]	183	1			T27	6		T227	36		T153	12
auto[1]	values[1]	values[4]	206	1			T16	12		T31	13		T263	11
auto[1]	values[1]	values[5]	168	1			T30	2		T69	12		T22	15
auto[1]	values[1]	values[6]	167	1			T1	26		T16	9		T27	12
auto[1]	values[1]	values[7]	185	1			T30	9		T22	14		T36	9
auto[1]	values[2]	values[0]	135	1			T29	4		T28	8		T69	25
auto[1]	values[2]	values[1]	178	1			T30	9		T183	11		T266	8
auto[1]	values[2]	values[2]	175	1			T1	10		T30	10		T22	10
auto[1]	values[2]	values[3]	189	1			T167	14		T22	10		T198	54
auto[1]	values[2]	values[4]	99	1			T31	6		T263	10		T322	4
auto[1]	values[2]	values[5]	107	1			T27	16		T323	2		T198	27
auto[1]	values[2]	values[6]	176	1			T16	10		T31	15		T183	8
auto[1]	values[2]	values[7]	143	1			T183	15		T129	8		T215	10
auto[1]	values[3]	values[0]	76	1			T1	8		T89	16		T173	5
auto[1]	values[3]	values[1]	196	1			T178	6		T22	7		T74	15
auto[1]	values[3]	values[2]	166	1			T27	3		T170	11		T190	8
auto[1]	values[3]	values[3]	84	1			T198	9		T47	8		T324	34
auto[1]	values[3]	values[4]	331	1			T16	8		T81	19		T227	2
auto[1]	values[3]	values[5]	165	1			T27	14		T69	11		T172	17
auto[1]	values[3]	values[6]	237	1			T27	9		T36	11		T170	5
auto[1]	values[3]	values[7]	66	1			T172	9		T129	9		T226	8
auto[1]	values[4]	values[0]	133	1			T35	14		T153	8		T256	81
auto[1]	values[4]	values[1]	360	1			T16	9		T198	13		T266	7
auto[1]	values[4]	values[2]	215	1			T30	19		T202	11		T183	25
auto[1]	values[4]	values[3]	154	1			T16	10		T27	8		T28	13
auto[1]	values[4]	values[4]	138	1			T227	11		T173	11		T244	10
auto[1]	values[4]	values[5]	135	1			T36	12		T160	6		T266	7
auto[1]	values[4]	values[6]	117	1			T28	32		T183	12		T190	6
auto[1]	values[4]	values[7]	120	1			T27	11		T220	11		T190	8
auto[1]	values[5]	values[0]	216	1			T30	7		T69	8		T35	8
auto[1]	values[5]	values[1]	153	1			T31	2		T313	13		T190	9
auto[1]	values[5]	values[2]	137	1			T153	21		T130	15		T133	9
auto[1]	values[5]	values[3]	128	1			T35	38		T215	13		T130	14
auto[1]	values[5]	values[4]	88	1			T16	13		T153	9		T234	7
auto[1]	values[5]	values[5]	98	1			T69	12		T71	14		T129	10
auto[1]	values[5]	values[6]	164	1			T16	3		T69	9		T170	17
auto[1]	values[5]	values[7]	161	1			T27	7		T172	12		T266	11
auto[1]	values[6]	values[0]	145	1			T27	16		T35	6		T36	9
auto[1]	values[6]	values[1]	101	1			T35	4		T71	8		T153	12
auto[1]	values[6]	values[2]	91	1			T30	18		T33	6		T183	14
auto[1]	values[6]	values[3]	177	1			T1	9		T81	27		T160	9
auto[1]	values[6]	values[4]	116	1			T30	9		T71	7		T153	8
auto[1]	values[6]	values[5]	100	1			T16	15		T263	8		T213	11
auto[1]	values[6]	values[6]	117	1			T325	2		T186	9		T266	5
auto[1]	values[6]	values[7]	122	1			T172	5		T129	13		T262	16
auto[1]	values[7]	values[0]	138	1			T30	8		T178	4		T160	38
auto[1]	values[7]	values[1]	115	1			T16	7		T31	15		T202	8
auto[1]	values[7]	values[2]	90	1			T1	8		T172	6		T153	6
auto[1]	values[7]	values[3]	141	1			T81	6		T189	12		T35	8
auto[1]	values[7]	values[4]	82	1			T202	21		T183	8		T195	2
auto[1]	values[7]	values[5]	103	1			T31	7		T186	18		T170	5
auto[1]	values[7]	values[6]	80	1			T170	33		T237	9		T233	8
auto[1]	values[7]	values[7]	106	1			T27	17		T31	10		T69	5