Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2218972	1			T1	15057		T2	1		T4	10429
all_pins[1]	2218972	1			T1	15057		T2	1		T4	10429
all_pins[2]	2218972	1			T1	15057		T2	1		T4	10429
all_pins[3]	2218972	1			T1	15057		T2	1		T4	10429
all_pins[4]	2218972	1			T1	15057		T2	1		T4	10429
all_pins[5]	2218972	1			T1	15057		T2	1		T4	10429
all_pins[6]	2218972	1			T1	15057		T2	1		T4	10429
all_pins[7]	2218972	1			T1	15057		T2	1		T4	10429

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	17627205	1			T1	120447		T2	8		T4	83432
values[0x1]	124571	1			T1	9		T16	35		T27	18319
transitions[0x0=>0x1]	123708	1			T1	8		T16	25		T27	18309
transitions[0x1=>0x0]	123717	1			T1	8		T16	25		T27	18309

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2218498	1			T1	15057		T2	1		T4	10429
all_pins[0]	values[0x1]	474	1			T16	6		T27	54		T30	3
all_pins[0]	transitions[0x0=>0x1]	366	1			T16	3		T27	50		T30	3
all_pins[0]	transitions[0x1=>0x0]	205	1			T1	2		T16	1		T55	1
all_pins[1]	values[0x0]	2218659	1			T1	15055		T2	1		T4	10429
all_pins[1]	values[0x1]	313	1			T1	2		T16	4		T27	4
all_pins[1]	transitions[0x0=>0x1]	256	1			T1	2		T16	2		T27	4
all_pins[1]	transitions[0x1=>0x0]	141	1			T16	2		T27	1		T30	3
all_pins[2]	values[0x0]	2218774	1			T1	15057		T2	1		T4	10429
all_pins[2]	values[0x1]	198	1			T16	4		T27	1		T30	3
all_pins[2]	transitions[0x0=>0x1]	152	1			T16	2		T27	1		T30	2
all_pins[2]	transitions[0x1=>0x0]	132	1			T1	2		T16	5		T27	3
all_pins[3]	values[0x0]	2218794	1			T1	15055		T2	1		T4	10429
all_pins[3]	values[0x1]	178	1			T1	2		T16	7		T27	3
all_pins[3]	transitions[0x0=>0x1]	134	1			T1	2		T16	5		T27	2
all_pins[3]	transitions[0x1=>0x0]	146	1			T16	3		T30	4		T55	1
all_pins[4]	values[0x0]	2218782	1			T1	15057		T2	1		T4	10429
all_pins[4]	values[0x1]	190	1			T16	5		T27	1		T30	4
all_pins[4]	transitions[0x0=>0x1]	144	1			T16	5		T30	1		T55	1
all_pins[4]	transitions[0x1=>0x0]	860	1			T1	2		T16	3		T30	1
all_pins[5]	values[0x0]	2218066	1			T1	15055		T2	1		T4	10429
all_pins[5]	values[0x1]	906	1			T1	2		T16	3		T27	1
all_pins[5]	transitions[0x0=>0x1]	436	1			T1	1		T16	2		T27	1
all_pins[5]	transitions[0x1=>0x0]	121645	1			T1	2		T16	2		T27	18251
all_pins[6]	values[0x0]	2096857	1			T1	15054		T2	1		T4	10429
all_pins[6]	values[0x1]	122115	1			T1	3		T16	3		T27	18251
all_pins[6]	transitions[0x0=>0x1]	122072	1			T1	3		T16	3		T27	18249
all_pins[6]	transitions[0x1=>0x0]	154	1			T16	3		T27	2		T69	2
all_pins[7]	values[0x0]	2218775	1			T1	15057		T2	1		T4	10429
all_pins[7]	values[0x1]	197	1			T16	3		T27	4		T69	2
all_pins[7]	transitions[0x0=>0x1]	148	1			T16	3		T27	2		T69	1
all_pins[7]	transitions[0x1=>0x0]	434	1			T16	6		T27	52		T30	3