Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	291	1			T16	2		T27	4		T28	1
auto[ReadAddrCrossIntoMailbox]	228	1			T1	2		T16	3		T27	3
auto[ReadAddrCrossOutOfMailbox]	248	1			T1	1		T15	2		T16	3
auto[ReadAddrCrossAllMailbox]	158	1			T1	1		T16	3		T27	1
auto[ReadAddrOutsideMailbox]	2865	1			T1	24		T2	4		T12	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1890

1

T1

19

T2

2

T12

2

auto[1]

1900

1

T1

9

T2

2

T12

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	663	1			T1	5		T16	7		T167	2
read_ops[0x0b]	642	1			T1	8		T16	6		T29	2
read_ops[0x3b]	610	1			T1	3		T2	4		T12	4
read_ops[0x6b]	654	1			T1	3		T16	11		T32	2
read_ops[0xbb]	608	1			T1	5		T16	14		T32	4
read_ops[0xeb]	613	1			T1	4		T16	11		T27	11

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T31	1		T69	1		T36	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	22	1			T16	1		T27	1		T30	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T181	1		T69	1		T153	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	16	1			T30	1		T181	1		T71	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T16	1		T27	1		T295	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T30	1		T178	1		T190	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T183	1		T173	1		T266	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T31	1		T178	1		T170	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	243	1			T1	4		T167	1		T27	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	260	1			T1	1		T16	5		T167	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T30	1		T22	1		T164	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T164	2		T71	1		T230	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T28	1		T220	1		T213	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T28	1		T30	1		T69	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T30	1		T35	1		T231	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T16	1		T27	1		T36	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T30	1		T22	1		T198	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T27	1		T28	1		T30	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	266	1			T1	6		T16	2		T29	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	211	1			T1	2		T16	3		T29	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T16	1		T27	1		T69	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T69	2		T22	1		T214	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T1	1		T16	1		T27	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T183	1		T227	1		T198	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T1	1		T15	1		T28	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T15	1		T69	2		T22	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T220	2		T213	1		T265	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	9	1			T36	1		T213	2		T291	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	228	1			T1	1		T2	2		T12	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	218	1			T2	2		T12	2		T16	4
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T22	1		T183	1		T295	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	22	1			T81	1		T173	1		T295	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	13	1			T16	1		T22	1		T202	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	14	1			T27	1		T30	1		T170	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T16	1		T27	1		T22	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T30	2		T190	1		T266	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T16	1		T35	1		T129	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T31	2		T71	1		T153	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	222	1			T1	1		T16	4		T32	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	285	1			T1	2		T16	4		T32	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	18	1			T27	1		T28	1		T202	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	18	1			T30	1		T160	1		T71	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T300	1		T22	2		T35	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T1	1		T16	1		T69	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	16	1			T31	1		T231	1		T198	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T30	1		T69	1		T231	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T1	1		T16	1		T22	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	7	1			T266	1		T267	1		T234	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	238	1			T1	1		T16	4		T32	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	236	1			T1	2		T16	8		T32	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T27	1		T31	1		T230	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	21	1			T30	1		T71	1		T230	3
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T27	1		T36	1		T170	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T35	1		T160	1		T172	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	16	1			T27	1		T170	1		T220	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T22	1		T202	1		T198	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T74	1		T227	1		T258	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T16	1		T30	1		T22	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	235	1			T1	3		T16	5		T27	7
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	223	1			T1	1		T16	5		T27	1