Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.32	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	1	127	99.22

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	1	127	99.22	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2965	1			T1	32		T16	47		T27	25
values[1]	3226	1			T68	8		T27	40		T28	44
values[2]	2664	1			T1	21		T16	20		T167	14
values[3]	3450	1			T1	20		T16	60		T27	42
values[4]	2912	1			T1	44		T12	6		T16	69
values[5]	3106	1			T1	20		T5	10		T16	45
values[6]	2956	1			T1	20		T2	18		T16	20
values[7]	3426	1			T15	2		T29	4		T180	6

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3103	1			T1	40		T2	18		T15	2
values[1]	3434	1			T12	6		T180	6		T27	42
values[2]	2936	1			T1	20		T16	20		T30	21
values[3]	3080	1			T1	45		T5	10		T16	48
values[4]	2859	1			T1	32		T16	60		T63	2
values[5]	3351	1			T16	20		T27	78		T30	30
values[6]	3273	1			T1	20		T16	92		T32	20
values[7]	2669	1			T167	14		T27	46		T28	113

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24308

1

T1

150

T2

18

T5

10

auto[1]

397

1

T1

7

T16

5

T27

5

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	1	127	99.22	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[1]]	[values[3]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	457	1			T181	6		T178	20		T182	24
auto[0]	values[0]	values[1]	359	1			T81	24		T183	19		T184	8
auto[0]	values[0]	values[2]	193	1			T185	8		T186	20		T187	12
auto[0]	values[0]	values[3]	301	1			T81	20		T172	24		T188	4
auto[0]	values[0]	values[4]	463	1			T1	29		T16	20		T27	24
auto[0]	values[0]	values[5]	229	1			T189	12		T160	20		T190	41
auto[0]	values[0]	values[6]	520	1			T16	25		T183	20		T129	20
auto[0]	values[0]	values[7]	385	1			T179	10		T69	20		T22	20
auto[0]	values[1]	values[0]	283	1			T27	20		T30	26		T191	2
auto[0]	values[1]	values[1]	567	1			T183	20		T173	20		T153	100
auto[0]	values[1]	values[2]	541	1			T192	19		T183	20		T193	106
auto[0]	values[1]	values[3]	277	1			T68	8		T194	18		T172	20
auto[0]	values[1]	values[4]	344	1			T31	18		T195	2		T153	84
auto[0]	values[1]	values[5]	457	1			T30	30		T83	20		T190	52
auto[0]	values[1]	values[6]	508	1			T27	20		T30	20		T97	4
auto[0]	values[1]	values[7]	218	1			T28	44		T196	22		T197	8
auto[0]	values[2]	values[0]	241	1			T28	19		T198	70		T199	29
auto[0]	values[2]	values[1]	387	1			T31	22		T200	12		T69	55
auto[0]	values[2]	values[2]	436	1			T30	19		T190	40		T201	6
auto[0]	values[2]	values[3]	446	1			T1	20		T30	24		T31	43
auto[0]	values[2]	values[4]	210	1			T16	20		T30	20		T69	20
auto[0]	values[2]	values[5]	326	1			T36	23		T172	20		T129	20
auto[0]	values[2]	values[6]	198	1			T170	46		T71	55		T129	20
auto[0]	values[2]	values[7]	370	1			T167	14		T31	26		T81	41
auto[0]	values[3]	values[0]	343	1			T202	27		T203	24		T204	14
auto[0]	values[3]	values[1]	419	1			T27	42		T89	16		T33	38
auto[0]	values[3]	values[2]	427	1			T1	18		T169	4		T205	20
auto[0]	values[3]	values[3]	542	1			T36	20		T160	20		T202	19
auto[0]	values[3]	values[4]	343	1			T16	19		T82	6		T33	20
auto[0]	values[3]	values[5]	536	1			T69	20		T206	4		T173	22
auto[0]	values[3]	values[6]	525	1			T16	39		T30	22		T69	20
auto[0]	values[3]	values[7]	254	1			T207	6		T208	18		T73	99
auto[0]	values[4]	values[0]	530	1			T1	19		T16	21		T209	22
auto[0]	values[4]	values[1]	467	1			T12	6		T22	24		T210	18
auto[0]	values[4]	values[2]	245	1			T211	10		T71	19		T74	20
auto[0]	values[4]	values[3]	261	1			T1	24		T16	48		T190	20
auto[0]	values[4]	values[4]	419	1			T27	21		T212	59		T213	20
auto[0]	values[4]	values[5]	238	1			T214	10		T35	28		T170	20
auto[0]	values[4]	values[6]	345	1			T27	23		T178	35		T35	46
auto[0]	values[4]	values[7]	360	1			T28	69		T30	20		T215	23
auto[0]	values[5]	values[0]	413	1			T1	20		T27	20		T96	4
auto[0]	values[5]	values[1]	473	1			T216	10		T217	16		T170	46
auto[0]	values[5]	values[2]	420	1			T16	20		T158	8		T218	4
auto[0]	values[5]	values[3]	329	1			T5	10		T84	16		T172	20
auto[0]	values[5]	values[4]	181	1			T63	2		T88	8		T27	20
auto[0]	values[5]	values[5]	590	1			T27	20		T69	82		T36	91
auto[0]	values[5]	values[6]	281	1			T16	25		T160	20		T219	6
auto[0]	values[5]	values[7]	369	1			T27	20		T168	18		T36	20
auto[0]	values[6]	values[0]	210	1			T2	18		T30	72		T213	20
auto[0]	values[6]	values[1]	419	1			T28	51		T220	21		T190	20
auto[0]	values[6]	values[2]	343	1			T221	18		T222	4		T164	6
auto[0]	values[6]	values[3]	337	1			T183	20		T223	10		T71	44
auto[0]	values[6]	values[4]	277	1			T171	65		T224	47		T225	22
auto[0]	values[6]	values[5]	496	1			T16	19		T27	57		T69	20
auto[0]	values[6]	values[6]	464	1			T1	20		T22	20		T35	19
auto[0]	values[6]	values[7]	364	1			T35	20		T172	26		T226	28
auto[0]	values[7]	values[0]	577	1			T15	2		T27	33		T30	20
auto[0]	values[7]	values[1]	287	1			T180	6		T95	6		T31	26
auto[0]	values[7]	values[2]	287	1			T31	21		T190	20		T227	42
auto[0]	values[7]	values[3]	530	1			T29	4		T69	39		T228	2
auto[0]	values[7]	values[4]	584	1			T229	2		T170	31		T198	20
auto[0]	values[7]	values[5]	426	1			T33	20		T35	18		T230	12
auto[0]	values[7]	values[6]	380	1			T32	20		T36	20		T202	19
auto[0]	values[7]	values[7]	301	1			T27	26		T42	27		T231	6
auto[1]	values[0]	values[0]	7	1			T129	2		T153	1		T232	1
auto[1]	values[0]	values[1]	13	1			T81	1		T183	1		T213	5
auto[1]	values[0]	values[2]	3	1			T215	1		T233	2		-	-
auto[1]	values[0]	values[3]	5	1			T234	3		T235	2		-	-
auto[1]	values[0]	values[4]	14	1			T1	3		T27	1		T198	1
auto[1]	values[0]	values[5]	3	1			T71	3		-	-		-	-
auto[1]	values[0]	values[6]	6	1			T16	2		T236	2		T203	1
auto[1]	values[0]	values[7]	7	1			T186	3		T73	2		T237	2
auto[1]	values[1]	values[0]	3	1			T153	2		T238	1		-	-
auto[1]	values[1]	values[1]	5	1			T239	1		T240	1		T241	1
auto[1]	values[1]	values[2]	3	1			T192	1		T242	1		T243	1
auto[1]	values[1]	values[4]	7	1			T31	2		T153	1		T203	1
auto[1]	values[1]	values[5]	2	1			T244	1		T245	1		-	-
auto[1]	values[1]	values[6]	8	1			T71	2		T198	1		T246	3
auto[1]	values[1]	values[7]	3	1			T233	3		-	-		-	-
auto[1]	values[2]	values[0]	6	1			T28	4		T247	1		T248	1
auto[1]	values[2]	values[1]	3	1			T69	1		T43	1		T249	1
auto[1]	values[2]	values[2]	4	1			T30	2		T213	1		T250	1
auto[1]	values[2]	values[3]	9	1			T1	1		T31	1		T34	6
auto[1]	values[2]	values[4]	3	1			T234	1		T240	2		-	-
auto[1]	values[2]	values[5]	11	1			T153	4		T251	3		T252	3
auto[1]	values[2]	values[6]	7	1			T170	1		T71	3		T253	1
auto[1]	values[2]	values[7]	7	1			T31	1		T236	1		T239	1
auto[1]	values[3]	values[0]	3	1			T203	1		T254	2		-	-
auto[1]	values[3]	values[1]	6	1			T33	1		T198	1		T244	1
auto[1]	values[3]	values[2]	8	1			T1	2		T172	1		T251	1
auto[1]	values[3]	values[3]	14	1			T202	1		T215	3		T255	1
auto[1]	values[3]	values[4]	7	1			T16	1		T81	1		T226	4
auto[1]	values[3]	values[5]	8	1			T133	1		T256	1		T240	1
auto[1]	values[3]	values[6]	11	1			T16	1		T35	1		T160	1
auto[1]	values[3]	values[7]	4	1			T257	4		-	-		-	-
auto[1]	values[4]	values[0]	11	1			T1	1		T215	2		T253	3
auto[1]	values[4]	values[1]	6	1			T129	1		T238	1		T242	1
auto[1]	values[4]	values[2]	10	1			T71	2		T227	1		T232	1
auto[1]	values[4]	values[3]	3	1			T73	1		T237	1		T246	1
auto[1]	values[4]	values[4]	1	1			T212	1		-	-		-	-
auto[1]	values[4]	values[5]	6	1			T35	1		T258	2		T259	2
auto[1]	values[4]	values[6]	5	1			T173	3		T260	2		-	-
auto[1]	values[4]	values[7]	5	1			T30	3		T261	2		-	-
auto[1]	values[5]	values[0]	9	1			T170	1		T160	2		T262	2
auto[1]	values[5]	values[1]	6	1			T170	1		T263	3		T245	1
auto[1]	values[5]	values[2]	9	1			T264	1		T265	1		T248	1
auto[1]	values[5]	values[3]	8	1			T266	2		T267	1		T237	2
auto[1]	values[5]	values[4]	1	1			T267	1		-	-		-	-
auto[1]	values[5]	values[5]	11	1			T69	1		T36	3		T198	2
auto[1]	values[5]	values[6]	3	1			T246	3		-	-		-	-
auto[1]	values[5]	values[7]	3	1			T266	1		T268	2		-	-
auto[1]	values[6]	values[0]	1	1			T234	1		-	-		-	-
auto[1]	values[6]	values[1]	11	1			T28	2		T220	1		T173	1
auto[1]	values[6]	values[2]	4	1			T74	2		T265	2		-	-
auto[1]	values[6]	values[3]	1	1			T215	1		-	-		-	-
auto[1]	values[6]	values[4]	1	1			T43	1		-	-		-	-
auto[1]	values[6]	values[5]	5	1			T16	1		T27	1		T269	2
auto[1]	values[6]	values[6]	8	1			T35	1		T227	2		T133	1
auto[1]	values[6]	values[7]	15	1			T130	4		T242	1		T261	3
auto[1]	values[7]	values[0]	9	1			T27	3		T30	1		T242	3
auto[1]	values[7]	values[1]	6	1			T173	4		T267	1		T270	1
auto[1]	values[7]	values[2]	3	1			T227	2		T237	1		-	-
auto[1]	values[7]	values[3]	17	1			T69	1		T170	1		T130	1
auto[1]	values[7]	values[4]	4	1			T129	1		T244	2		T249	1
auto[1]	values[7]	values[5]	7	1			T35	2		T153	1		T236	2
auto[1]	values[7]	values[6]	4	1			T202	1		T271	2		T272	1
auto[1]	values[7]	values[7]	4	1			T245	4		-	-		-	-