Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1748

1

T1

6

T4

8

T9

4

auto[1]

1804

1

T1

14

T4

11

T9

2

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1956

1

T1

12

T4

19

T16

20

auto[1]

1596

1

T1

8

T9

6

T13

20

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2780

1

T1

11

T4

14

T9

6

auto[1]

772

1

T1

9

T4

5

T16

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	701	1			T1	7		T4	2		T9	2
valid[1]	719	1			T1	3		T4	2		T9	2
valid[2]	686	1			T1	2		T4	3		T9	1
valid[3]	716	1			T1	4		T4	5		T9	1
valid[4]	730	1			T1	4		T4	7		T13	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	107	1			T4	1		T16	1		T30	1
auto[0]	auto[0]	valid[0]	auto[1]	156	1			T9	2		T13	1		T18	3
auto[0]	auto[0]	valid[1]	auto[0]	117	1			T4	1		T16	4		T20	2
auto[0]	auto[0]	valid[1]	auto[1]	170	1			T13	3		T18	1		T40	1
auto[0]	auto[0]	valid[2]	auto[0]	126	1			T16	2		T20	1		T340	2
auto[0]	auto[0]	valid[2]	auto[1]	142	1			T1	1		T9	1		T13	3
auto[0]	auto[0]	valid[3]	auto[0]	134	1			T1	1		T4	3		T16	1
auto[0]	auto[0]	valid[3]	auto[1]	155	1			T9	1		T13	2		T18	1
auto[0]	auto[0]	valid[4]	auto[0]	109	1			T4	1		T20	1		T27	1
auto[0]	auto[0]	valid[4]	auto[1]	157	1			T13	3		T18	2		T79	2
auto[0]	auto[1]	valid[0]	auto[0]	120	1			T1	1		T21	1		T340	2
auto[0]	auto[1]	valid[0]	auto[1]	167	1			T1	2		T13	3		T18	2
auto[0]	auto[1]	valid[1]	auto[0]	119	1			T16	2		T20	2		T30	1
auto[0]	auto[1]	valid[1]	auto[1]	169	1			T1	1		T9	2		T13	2
auto[0]	auto[1]	valid[2]	auto[0]	104	1			T4	1		T16	2		T20	2
auto[0]	auto[1]	valid[2]	auto[1]	161	1			T1	1		T13	1		T16	1
auto[0]	auto[1]	valid[3]	auto[0]	108	1			T1	1		T4	2		T16	2
auto[0]	auto[1]	valid[3]	auto[1]	153	1			T13	2		T79	2		T80	1
auto[0]	auto[1]	valid[4]	auto[0]	140	1			T4	5		T16	2		T20	1
auto[0]	auto[1]	valid[4]	auto[1]	166	1			T1	3		T18	1		T79	3
auto[1]	auto[0]	valid[0]	auto[0]	70	1			T1	2		T16	1		T40	1
auto[1]	auto[0]	valid[1]	auto[0]	79	1			T1	1		T16	2		T30	1
auto[1]	auto[0]	valid[2]	auto[0]	73	1			T4	2		T31	1		T342	1
auto[1]	auto[0]	valid[3]	auto[0]	86	1			T1	1		T20	1		T21	2
auto[1]	auto[0]	valid[4]	auto[0]	67	1			T20	1		T27	1		T31	1
auto[1]	auto[1]	valid[0]	auto[0]	81	1			T1	2		T4	1		T20	1
auto[1]	auto[1]	valid[1]	auto[0]	65	1			T1	1		T4	1		T30	1
auto[1]	auto[1]	valid[2]	auto[0]	80	1			T41	1		T340	1		T55	1
auto[1]	auto[1]	valid[3]	auto[0]	80	1			T1	1		T27	1		T31	3
auto[1]	auto[1]	valid[4]	auto[0]	91	1			T1	1		T4	1		T16	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal