Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
96.77 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 14 0 14 100.00
Crosses 48 2 46 95.83


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 8 0 8 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 48 2 46 95.83 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 853 1 T1 4 T16 14 T27 10
all_values[1] 853 1 T1 4 T16 14 T27 10
all_values[2] 853 1 T1 4 T16 14 T27 10
all_values[3] 853 1 T1 4 T16 14 T27 10
all_values[4] 853 1 T1 4 T16 14 T27 10
all_values[5] 853 1 T1 4 T16 14 T27 10
all_values[6] 853 1 T1 4 T16 14 T27 10
all_values[7] 853 1 T1 4 T16 14 T27 10



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3586 1 T1 18 T16 54 T27 36
auto[1] 3238 1 T1 14 T16 58 T27 44



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2762 1 T1 13 T16 40 T27 33
auto[1] 4062 1 T1 19 T16 72 T27 47



Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3910 1 T1 19 T16 63 T27 45
auto[1] 2914 1 T1 13 T16 49 T27 35



Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 48 2 46 95.83 2
Automatically Generated Cross Bins 48 2 46 95.83 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[5]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 163 1 T1 2 T27 1 T30 1
all_values[0] auto[0] auto[0] auto[1] 75 1 T1 1 T16 1 T27 1
all_values[0] auto[0] auto[1] auto[0] 152 1 T16 4 T27 2 T30 2
all_values[0] auto[0] auto[1] auto[1] 94 1 T16 5 T27 2 T30 2
all_values[0] auto[1] auto[0] auto[1] 189 1 T1 1 T16 2 T27 1
all_values[0] auto[1] auto[1] auto[1] 180 1 T16 2 T27 3 T30 3
all_values[1] auto[0] auto[0] auto[0] 179 1 T16 2 T27 3 T30 1
all_values[1] auto[0] auto[0] auto[1] 77 1 T1 1 T27 1 T30 2
all_values[1] auto[0] auto[1] auto[0] 137 1 T16 2 T27 1 T30 4
all_values[1] auto[0] auto[1] auto[1] 85 1 T1 1 T16 2 T27 1
all_values[1] auto[1] auto[0] auto[1] 174 1 T1 1 T16 3 T27 1
all_values[1] auto[1] auto[1] auto[1] 201 1 T1 1 T16 5 T27 3
all_values[2] auto[0] auto[0] auto[0] 185 1 T1 2 T16 5 T27 4
all_values[2] auto[0] auto[0] auto[1] 86 1 T16 1 T27 1 T30 3
all_values[2] auto[0] auto[1] auto[0] 139 1 T1 1 T16 2 T30 1
all_values[2] auto[0] auto[1] auto[1] 80 1 T16 2 T55 1 T69 3
all_values[2] auto[1] auto[0] auto[1] 192 1 T16 2 T27 2 T30 2
all_values[2] auto[1] auto[1] auto[1] 171 1 T1 1 T16 2 T27 3
all_values[3] auto[0] auto[0] auto[0] 198 1 T1 2 T16 1 T27 1
all_values[3] auto[0] auto[0] auto[1] 80 1 T16 3 T30 3 T69 3
all_values[3] auto[0] auto[1] auto[0] 163 1 T27 1 T30 1 T55 3
all_values[3] auto[0] auto[1] auto[1] 76 1 T1 1 T16 1 T27 2
all_values[3] auto[1] auto[0] auto[1] 184 1 T16 4 T27 3 T30 2
all_values[3] auto[1] auto[1] auto[1] 152 1 T1 1 T16 5 T27 3
all_values[4] auto[0] auto[0] auto[0] 192 1 T1 2 T16 3 T27 3
all_values[4] auto[0] auto[0] auto[1] 89 1 T1 1 T16 1 T27 1
all_values[4] auto[0] auto[1] auto[0] 140 1 T16 1 T27 3 T30 2
all_values[4] auto[0] auto[1] auto[1] 72 1 T16 1 T30 1 T69 5
all_values[4] auto[1] auto[0] auto[1] 206 1 T1 1 T16 5 T27 1
all_values[4] auto[1] auto[1] auto[1] 154 1 T16 3 T27 2 T30 3
all_values[5] auto[0] auto[0] auto[0] 250 1 T1 1 T16 5 T27 4
all_values[5] auto[0] auto[1] auto[0] 211 1 T1 1 T16 5 T27 2
all_values[5] auto[1] auto[0] auto[1] 200 1 T1 1 T16 1 T27 1
all_values[5] auto[1] auto[1] auto[1] 192 1 T1 1 T16 3 T27 3
all_values[6] auto[0] auto[0] auto[0] 181 1 T16 1 T27 3 T30 4
all_values[6] auto[0] auto[0] auto[1] 73 1 T16 2 T27 1 T69 2
all_values[6] auto[0] auto[1] auto[0] 149 1 T16 2 T27 1 T30 1
all_values[6] auto[0] auto[1] auto[1] 90 1 T1 1 T16 1 T27 1
all_values[6] auto[1] auto[0] auto[1] 184 1 T16 4 T27 2 T30 5
all_values[6] auto[1] auto[1] auto[1] 176 1 T1 3 T16 4 T27 2
all_values[7] auto[0] auto[0] auto[0] 165 1 T16 4 T27 1 T30 6
all_values[7] auto[0] auto[0] auto[1] 76 1 T16 2 T55 1 T69 4
all_values[7] auto[0] auto[1] auto[0] 158 1 T1 2 T16 3 T27 3
all_values[7] auto[0] auto[1] auto[1] 95 1 T16 1 T27 1 T166 1
all_values[7] auto[1] auto[0] auto[1] 188 1 T1 2 T16 2 T30 1
all_values[7] auto[1] auto[1] auto[1] 171 1 T16 2 T27 5 T30 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%