Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49312

1

T1

314

T4

460

T6

12

auto[1]

17119

1

T1

78

T9

98

T13

227

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48262

1

T1

248

T4

317

T6

8

auto[1]

18169

1

T1

144

T4

143

T6

4

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34140	1			T1	191		T4	238		T6	8
others[1]	5645	1			T1	41		T4	36		T9	8
others[2]	5576	1			T1	38		T4	39		T6	2
others[3]	6443	1			T1	44		T4	45		T6	1
interest[1]	3596	1			T1	17		T4	21		T9	4
interest[4]	22390	1			T1	129		T4	159		T6	7
interest[64]	11031	1			T1	61		T4	81		T6	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15935	1			T1	82		T4	168		T6	4
auto[0]	auto[0]	others[1]	2650	1			T1	16		T4	23		T16	29
auto[0]	auto[0]	others[2]	2663	1			T1	17		T4	25		T6	2
auto[0]	auto[0]	others[3]	3014	1			T1	21		T4	29		T6	1
auto[0]	auto[0]	interest[1]	1713	1			T1	6		T4	15		T16	15
auto[0]	auto[0]	interest[4]	10450	1			T1	54		T4	120		T6	3
auto[0]	auto[0]	interest[64]	5168	1			T1	28		T4	57		T6	1
auto[0]	auto[1]	others[0]	8884	1			T1	33		T9	51		T13	114
auto[0]	auto[1]	others[1]	1481	1			T1	12		T9	8		T13	24
auto[0]	auto[1]	others[2]	1359	1			T1	9		T9	12		T13	19
auto[0]	auto[1]	others[3]	1642	1			T1	10		T9	12		T13	24
auto[0]	auto[1]	interest[1]	912	1			T1	3		T9	4		T13	15
auto[0]	auto[1]	interest[4]	5886	1			T1	24		T9	32		T13	79
auto[0]	auto[1]	interest[64]	2841	1			T1	11		T9	11		T13	31
auto[1]	auto[0]	others[0]	9321	1			T1	76		T4	70		T6	4
auto[1]	auto[0]	others[1]	1514	1			T1	13		T4	13		T16	11
auto[1]	auto[0]	others[2]	1554	1			T1	12		T4	14		T16	9
auto[1]	auto[0]	others[3]	1787	1			T1	13		T4	16		T16	12
auto[1]	auto[0]	interest[1]	971	1			T1	8		T4	6		T16	5
auto[1]	auto[0]	interest[4]	6054	1			T1	51		T4	39		T6	4
auto[1]	auto[0]	interest[64]	3022	1			T1	22		T4	24		T16	25

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal