Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2779084	1			T1	1614		T3	1702		T4	1
all_values[1]	2779084	1			T1	1614		T3	1702		T4	1
all_values[2]	2779084	1			T1	1614		T3	1702		T4	1
all_values[3]	2779084	1			T1	1614		T3	1702		T4	1
all_values[4]	2779084	1			T1	1614		T3	1702		T4	1
all_values[5]	2779084	1			T1	1614		T3	1702		T4	1
all_values[6]	2779084	1			T1	1614		T3	1702		T4	1
all_values[7]	2779084	1			T1	1614		T3	1702		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21957808

1

T1

12912

T3

13616

T4

8

auto[1]

274864

1

T26

108

T30

49

T64

39

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22211147

1

T1

12829

T3

13616

T4

8

auto[1]

21525

1

T1

83

T8

96

T9

6

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2728116	1			T1	1566		T3	1702		T4	1
all_values[0]	auto[0]	auto[1]	11063	1			T1	48		T8	48		T26	179
all_values[0]	auto[1]	auto[0]	39154	1			T26	5		T64	5		T69	8
all_values[0]	auto[1]	auto[1]	751	1			T26	4		T30	4		T64	1
all_values[1]	auto[0]	auto[0]	2732918	1			T1	1579		T3	1702		T4	1
all_values[1]	auto[0]	auto[1]	4941	1			T1	35		T8	36		T26	66
all_values[1]	auto[1]	auto[0]	40721	1			T26	4		T30	3		T64	2
all_values[1]	auto[1]	auto[1]	504	1			T26	5		T30	4		T64	2
all_values[2]	auto[0]	auto[0]	2735675	1			T1	1614		T3	1702		T4	1
all_values[2]	auto[0]	auto[1]	1885	1			T8	12		T26	6		T30	14
all_values[2]	auto[1]	auto[0]	41254	1			T26	8		T30	5		T64	5
all_values[2]	auto[1]	auto[1]	270	1			T26	7		T30	5		T64	1
all_values[3]	auto[0]	auto[0]	2747287	1			T1	1614		T3	1702		T4	1
all_values[3]	auto[0]	auto[1]	218	1			T26	4		T30	3		T64	1
all_values[3]	auto[1]	auto[0]	31383	1			T26	16		T30	2		T64	4
all_values[3]	auto[1]	auto[1]	196	1			T26	4		T30	2		T64	2
all_values[4]	auto[0]	auto[0]	2756587	1			T1	1614		T3	1702		T4	1
all_values[4]	auto[0]	auto[1]	195	1			T26	3		T30	4		T64	1
all_values[4]	auto[1]	auto[0]	22081	1			T26	7		T30	5		T64	5
all_values[4]	auto[1]	auto[1]	221	1			T26	4		T64	3		T69	1
all_values[5]	auto[0]	auto[0]	2749449	1			T1	1614		T3	1702		T4	1
all_values[5]	auto[0]	auto[1]	342	1			T9	6		T26	5		T47	5
all_values[5]	auto[1]	auto[0]	29128	1			T26	9		T30	5		T69	3
all_values[5]	auto[1]	auto[1]	165	1			T26	4		T69	3		T70	4
all_values[6]	auto[0]	auto[0]	2744386	1			T1	1614		T3	1702		T4	1
all_values[6]	auto[0]	auto[1]	185	1			T26	7		T30	3		T64	2
all_values[6]	auto[1]	auto[0]	34312	1			T26	13		T30	1		T64	2
all_values[6]	auto[1]	auto[1]	201	1			T26	3		T30	4		T64	3
all_values[7]	auto[0]	auto[0]	2744355	1			T1	1614		T3	1702		T4	1
all_values[7]	auto[0]	auto[1]	206	1			T26	6		T30	3		T69	2
all_values[7]	auto[1]	auto[0]	34341	1			T26	11		T30	7		T64	4
all_values[7]	auto[1]	auto[1]	182	1			T26	4		T30	2		T69	1