Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	31630	1			T1	77		T3	45		T5	2
auto[SpiFlashAddrCfg]	6893	1			T1	22		T3	17		T8	22
auto[SpiFlashAddr3b]	8105	1			T1	26		T3	30		T8	31
auto[SpiFlashAddr4b]	6624	1			T1	26		T3	14		T8	21

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30482

1

T1

62

T3

69

T7

4

auto[1]

22770

1

T1

89

T3

37

T5

2

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27947

1

T1

79

T3

56

T5

2

auto[1]

25305

1

T1

72

T3

50

T8

69

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	35668	1			T1	98		T3	59		T5	2
values[1]	1039	1			T1	8		T3	1		T8	3
values[2]	1265	1			T1	3		T8	8		T21	10
values[3]	1259	1			T1	5		T3	6		T8	3
values[4]	1348	1			T1	6		T3	2		T8	6
values[5]	1229	1			T1	4		T3	1		T8	6
values[6]	1293	1			T1	1		T3	3		T8	5
values[7]	1241	1			T1	3		T3	4		T8	5
values[8]	8910	1			T1	23		T3	30		T8	29

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30565

1

T5

2

T7

4

T8

172

auto[1]

22687

1

T1

151

T3

106

T19

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

51343

1

T1

144

T3

105

T5

2

write

1909

1

T1

7

T3

1

T8

8

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

17329

1

T1

58

T3

48

T7

4

valids[0x1]

35923

1

T1

93

T3

58

T5

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1281	1			T1	5		T3	1		T8	2
internal_process_ops[0x5a]	1426	1			T1	5		T3	6		T8	3
internal_process_ops[0x05]	19693	1			T1	35		T3	13		T5	2
internal_process_ops[0x35]	1346	1			T1	9		T3	4		T8	1
internal_process_ops[0x15]	1396	1			T1	4		T3	4		T8	5
internal_process_ops[0x03]	983	1			T1	2		T3	2		T8	4
internal_process_ops[0x0b]	983	1			T1	1		T3	2		T8	2
internal_process_ops[0x3b]	979	1			T1	3		T3	1		T8	6
internal_process_ops[0x6b]	981	1			T1	1		T8	2		T40	2
internal_process_ops[0xbb]	1018	1			T1	1		T3	2		T8	8
internal_process_ops[0xeb]	973	1			T1	1		T3	2		T8	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52347

1

T1

147

T3

106

T5

2

auto[1]

905

1

T1

4

T8

5

T21

16

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51455

1

T1

146

T3

104

T5

2

auto[1]

1797

1

T1

5

T3

2

T8

6

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10903

1

T7

4

T8

46

T10

20

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6074

1

T5

2

T8

51

T25

24

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2145

1

T8

12

T46

4

T33

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1861

1

T8

10

T25

11

T29

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2482

1

T8

15

T11

6

T20

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2173

1

T8

13

T25

8

T30

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2104

1

T8

8

T10

8

T28

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1757

1

T8

9

T25

26

T29

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

70

1

T8

1

T165

2

T32

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

49

1

T25

2

T34

2

T38

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

56

1

T166

2

T167

1

T41

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

71

1

T25

1

T34

1

T35

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

88

1

T35

1

T32

1

T37

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

59

1

T25

1

T34

1

T37

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

61

1

T48

1

T37

1

T39

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

63

1

T25

2

T29

2

T36

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

83

1

T38

2

T39

2

T168

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

67

1

T8

3

T34

1

T32

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

60

1

T25

1

T34

2

T35

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

71

1

T34

1

T35

1

T32

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

99

1

T8

2

T30

1

T39

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

62

1

T34

2

T39

2

T166

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

57

1

T25

2

T48

1

T37

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

50

1

T8

2

T30

1

T34

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

7875

1

T1

26

T3

34

T21

441

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6342

1

T1

49

T3

11

T21

216

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1242

1

T1

12

T3

10

T19

3

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1171

1

T1

8

T3

7

T21

14

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1511

1

T1

11

T3

19

T21

23

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1401

1

T1

15

T3

11

T21

22

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1223

1

T1

8

T3

6

T40

2

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1079

1

T1

15

T3

7

T21

25

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

52

1

T1

2

T26

1

T30

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

41

1

T21

7

T37

2

T169

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

48

1

T30

1

T49

2

T37

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

49

1

T27

1

T170

1

T169

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

61

1

T21

2

T27

1

T64

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

54

1

T21

1

T26

1

T27

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

50

1

T21

2

T30

2

T37

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

38

1

T1

2

T26

1

T27

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

61

1

T21

1

T26

1

T30

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

69

1

T26

1

T64

4

T171

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

53

1

T27

1

T37

1

T170

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

74

1

T21

4

T26

3

T30

6

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

52

1

T1

1

T21

3

T26

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

30

1

T1

2

T21

1

T49

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

53

1

T3

1

T21

3

T26

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

58

1

T21

3

T30

1

T37

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4006	1			T7	4		T8	25		T10	20
auto[0]	values[0]	valids[0x1]	15605	1			T5	2		T8	82		T11	14
auto[0]	values[1]	valids[0x1]	598	1			T8	3		T25	11		T30	6
auto[0]	values[2]	valids[0x0]	503	1			T8	6		T25	1		T30	2
auto[0]	values[2]	valids[0x1]	263	1			T8	2		T25	3		T48	2
auto[0]	values[3]	valids[0x0]	508	1			T8	3		T25	2		T30	2
auto[0]	values[3]	valids[0x1]	275	1			T25	3		T29	2		T34	1
auto[0]	values[4]	valids[0x0]	571	1			T8	4		T33	4		T25	5
auto[0]	values[4]	valids[0x1]	290	1			T8	2		T25	4		T48	2
auto[0]	values[5]	valids[0x0]	517	1			T8	4		T10	8		T29	2
auto[0]	values[5]	valids[0x1]	276	1			T8	2		T20	2		T25	3
auto[0]	values[6]	valids[0x0]	511	1			T8	2		T25	1		T29	4
auto[0]	values[6]	valids[0x1]	301	1			T8	3		T25	3		T30	2
auto[0]	values[7]	valids[0x0]	503	1			T8	3		T28	4		T25	5
auto[0]	values[7]	valids[0x1]	279	1			T8	2		T25	3		T158	2
auto[0]	values[8]	valids[0x0]	3462	1			T8	19		T28	4		T25	14
auto[0]	values[8]	valids[0x1]	2097	1			T8	10		T46	4		T33	2
auto[1]	values[0]	valids[0x0]	3090	1			T1	23		T3	25		T21	51
auto[1]	values[0]	valids[0x1]	12967	1			T1	75		T3	34		T21	646
auto[1]	values[1]	valids[0x1]	441	1			T1	8		T3	1		T21	7
auto[1]	values[2]	valids[0x0]	310	1			T1	3		T21	8		T43	1
auto[1]	values[2]	valids[0x1]	189	1			T21	2		T26	3		T27	7
auto[1]	values[3]	valids[0x0]	261	1			T1	5		T21	4		T26	6
auto[1]	values[3]	valids[0x1]	215	1			T3	6		T21	5		T26	2
auto[1]	values[4]	valids[0x0]	273	1			T1	3		T3	1		T40	2
auto[1]	values[4]	valids[0x1]	214	1			T1	3		T3	1		T21	1
auto[1]	values[5]	valids[0x0]	257	1			T1	3		T21	6		T26	1
auto[1]	values[5]	valids[0x1]	179	1			T1	1		T3	1		T21	1
auto[1]	values[6]	valids[0x0]	317	1			T1	1		T3	1		T19	1
auto[1]	values[6]	valids[0x1]	164	1			T3	2		T21	2		T26	2
auto[1]	values[7]	valids[0x0]	271	1			T1	3		T3	2		T19	2
auto[1]	values[7]	valids[0x1]	188	1			T3	2		T21	2		T26	1
auto[1]	values[8]	valids[0x0]	1969	1			T1	17		T3	19		T42	1
auto[1]	values[8]	valids[0x1]	1382	1			T1	6		T3	11		T21	27