Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
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Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv



Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 0 16 100.00
Crosses 72 0 72 100.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_busy_bit 2 0 2 100.00 100 1 1 2
cp_is_host_read 2 0 2 100.00 100 1 1 2
cp_other_status 8 0 8 100.00 100 1 1 8
cp_sw_read_while_csb_active 2 0 2 100.00 100 1 1 2
cp_wel_bit 2 0 2 100.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all_except_csb 64 0 64 100.00 100 1 1 0
cr_busyXwelXcsb 8 0 8 100.00 100 1 1 0


Summary for Variable cp_busy_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_busy_bit

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3187912 1 T1 4538 T3 5910 T5 1
auto[1] 18232 1 T1 31 T3 6 T8 52



Summary for Variable cp_is_host_read

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_is_host_read

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1021991 1 T1 39 T3 20 T5 1
auto[1] 2184153 1 T1 4530 T3 5896 T8 7702



Summary for Variable cp_other_status

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 8 0 8 100.00


Automatically Generated Bins for cp_other_status

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:524287] 547216 1 T1 1040 T3 1 T5 1
auto[524288:1048575] 346031 1 T1 259 T3 5 T6 39
auto[1048576:1572863] 357363 1 T1 800 T3 605 T6 428
auto[1572864:2097151] 356696 1 T1 1 T3 1829 T6 1
auto[2097152:2621439] 438439 1 T1 531 T3 3475 T8 2652
auto[2621440:3145727] 390859 1 T1 4 T7 322 T15 159
auto[3145728:3670015] 428759 1 T1 905 T6 337 T8 1155
auto[3670016:4194303] 340781 1 T1 1029 T3 1 T6 426



Summary for Variable cp_sw_read_while_csb_active

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sw_read_while_csb_active

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2202817 1 T1 4568 T3 5914 T5 1
auto[1] 1003327 1 T1 1 T3 2 T6 1190



Summary for Variable cp_wel_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_wel_bit

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2805853 1 T1 4311 T3 3452 T5 1
auto[1] 400291 1 T1 258 T3 2464 T8 2659



Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for cr_all_except_csb

Bins
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0:524287] auto[0] 200511 1 T1 6 T3 1 T5 1
auto[0] auto[0] auto[0:524287] auto[1] 308445 1 T1 773 T8 514 T11 1140
auto[0] auto[0] auto[524288:1048575] auto[0] 100403 1 T1 2 T3 1 T6 39
auto[0] auto[0] auto[524288:1048575] auto[1] 186758 1 T1 256 T3 4 T8 1
auto[0] auto[0] auto[1048576:1572863] auto[0] 99309 1 T1 10 T3 2 T6 428
auto[0] auto[0] auto[1048576:1572863] auto[1] 199669 1 T1 770 T3 347 T11 515
auto[0] auto[0] auto[1572864:2097151] auto[0] 106082 1 T1 1 T3 7 T6 1
auto[0] auto[0] auto[1572864:2097151] auto[1] 216291 1 T3 1822 T8 385 T11 1
auto[0] auto[0] auto[2097152:2621439] auto[0] 136253 1 T1 2 T3 4 T10 793
auto[0] auto[0] auto[2097152:2621439] auto[1] 236724 1 T1 529 T3 1257 T11 2124
auto[0] auto[0] auto[2621440:3145727] auto[0] 123730 1 T7 322 T15 159 T20 3153
auto[0] auto[0] auto[2621440:3145727] auto[1] 213598 1 T1 4 T20 2938 T21 2610
auto[0] auto[0] auto[3145728:3670015] auto[0] 144312 1 T1 7 T6 337 T8 3
auto[0] auto[0] auto[3145728:3670015] auto[1] 214830 1 T1 892 T8 1152 T20 2
auto[0] auto[0] auto[3670016:4194303] auto[0] 106360 1 T1 4 T3 1 T6 426
auto[0] auto[0] auto[3670016:4194303] auto[1] 197377 1 T1 1024 T8 2953 T11 2764
auto[0] auto[1] auto[0:524287] auto[0] 593 1 T8 1 T10 123 T145 78
auto[0] auto[1] auto[0:524287] auto[1] 35239 1 T1 256 T8 1 T21 895
auto[0] auto[1] auto[524288:1048575] auto[0] 237 1 T1 1 T10 8 T27 2
auto[0] auto[1] auto[524288:1048575] auto[1] 56398 1 T27 256 T30 19 T32 2931
auto[0] auto[1] auto[1048576:1572863] auto[0] 413 1 T8 2 T26 1 T30 3
auto[0] auto[1] auto[1048576:1572863] auto[1] 55475 1 T3 256 T21 654 T37 2
auto[0] auto[1] auto[1572864:2097151] auto[0] 185 1 T21 3 T27 1 T25 2
auto[0] auto[1] auto[1572864:2097151] auto[1] 31274 1 T21 262 T27 641 T25 11
auto[0] auto[1] auto[2097152:2621439] auto[0] 361 1 T3 2 T8 2 T10 17
auto[0] auto[1] auto[2097152:2621439] auto[1] 63314 1 T3 2206 T8 2650 T49 259
auto[0] auto[1] auto[2621440:3145727] auto[0] 924 1 T145 1 T21 3 T27 1
auto[0] auto[1] auto[2621440:3145727] auto[1] 50635 1 T49 259 T230 256 T37 2668
auto[0] auto[1] auto[3145728:3670015] auto[0] 261 1 T21 2 T25 1 T30 3
auto[0] auto[1] auto[3145728:3670015] auto[1] 66665 1 T21 2 T30 863 T49 1
auto[0] auto[1] auto[3670016:4194303] auto[0] 255 1 T1 1 T21 1 T26 1
auto[0] auto[1] auto[3670016:4194303] auto[1] 35031 1 T21 845 T26 385 T30 512
auto[1] auto[0] auto[0:524287] auto[0] 241 1 T1 2 T8 2 T21 1
auto[1] auto[0] auto[0:524287] auto[1] 1953 1 T1 3 T8 21 T21 4
auto[1] auto[0] auto[524288:1048575] auto[0] 184 1 T8 1 T21 4 T26 5
auto[1] auto[0] auto[524288:1048575] auto[1] 1712 1 T8 5 T21 133 T26 18
auto[1] auto[0] auto[1048576:1572863] auto[0] 180 1 T1 2 T21 1 T26 3
auto[1] auto[0] auto[1048576:1572863] auto[1] 1885 1 T1 18 T21 72 T26 5
auto[1] auto[0] auto[1572864:2097151] auto[0] 191 1 T8 1 T21 1 T25 3
auto[1] auto[0] auto[1572864:2097151] auto[1] 2214 1 T8 18 T21 30 T25 6
auto[1] auto[0] auto[2097152:2621439] auto[0] 173 1 T3 2 T26 5 T27 2
auto[1] auto[0] auto[2097152:2621439] auto[1] 1213 1 T3 4 T26 9 T27 48
auto[1] auto[0] auto[2621440:3145727] auto[0] 156 1 T21 8 T26 1 T30 3
auto[1] auto[0] auto[2621440:3145727] auto[1] 1427 1 T21 169 T26 1 T30 2
auto[1] auto[0] auto[3145728:3670015] auto[0] 201 1 T1 1 T30 5 T49 2
auto[1] auto[0] auto[3145728:3670015] auto[1] 2143 1 T1 5 T30 4 T49 73
auto[1] auto[0] auto[3670016:4194303] auto[0] 158 1 T8 1 T21 4 T26 3
auto[1] auto[0] auto[3670016:4194303] auto[1] 1170 1 T21 81 T26 12 T49 2
auto[1] auto[1] auto[0:524287] auto[0] 44 1 T8 1 T49 2 T34 2
auto[1] auto[1] auto[0:524287] auto[1] 190 1 T8 2 T49 40 T64 12
auto[1] auto[1] auto[524288:1048575] auto[0] 35 1 T30 3 T32 2 T41 1
auto[1] auto[1] auto[524288:1048575] auto[1] 304 1 T32 2 T238 3 T237 25
auto[1] auto[1] auto[1048576:1572863] auto[0] 33 1 T37 1 T39 1 T164 1
auto[1] auto[1] auto[1048576:1572863] auto[1] 399 1 T37 3 T39 40 T164 1
auto[1] auto[1] auto[1572864:2097151] auto[0] 31 1 T21 1 T30 1 T37 1
auto[1] auto[1] auto[1572864:2097151] auto[1] 428 1 T21 40 T37 19 T38 8
auto[1] auto[1] auto[2097152:2621439] auto[0] 47 1 T49 3 T37 1 T70 2
auto[1] auto[1] auto[2097152:2621439] auto[1] 354 1 T49 39 T37 10 T70 5
auto[1] auto[1] auto[2621440:3145727] auto[0] 44 1 T37 1 T41 2 T188 2
auto[1] auto[1] auto[2621440:3145727] auto[1] 345 1 T37 38 T41 1 T188 1
auto[1] auto[1] auto[3145728:3670015] auto[0] 42 1 T49 1 T34 1 T39 2
auto[1] auto[1] auto[3145728:3670015] auto[1] 305 1 T49 18 T34 2 T39 47
auto[1] auto[1] auto[3670016:4194303] auto[0] 42 1 T26 1 T37 1 T210 2
auto[1] auto[1] auto[3670016:4194303] auto[1] 388 1 T26 1 T37 4 T210 1



Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 1788838 1 T1 4279 T3 3446 T5 1
auto[0] auto[0] auto[1] 1001814 1 T1 1 T6 1190 T7 840
auto[0] auto[1] auto[0] 396063 1 T1 258 T3 2464 T8 2656
auto[0] auto[1] auto[1] 1197 1 T10 140 T94 1 T49 3
auto[1] auto[0] auto[0] 14936 1 T1 31 T3 4 T8 49
auto[1] auto[0] auto[1] 265 1 T3 2 T21 1 T30 1
auto[1] auto[1] auto[0] 2980 1 T8 3 T21 41 T26 2
auto[1] auto[1] auto[1] 51 1 T30 1 T49 2 T37 2

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